Design, verification, and test of a true single-phase 8-bit adiabatic multiplier

Abstract

In this paper we present the design and experimental evaluation of an an 8-bit adiabatic multiplier with built-in self-test (BIST) logic and an internal single-phase sinusoidal power-clock generator: Both the multiplier and the BIST have been designed in SCAL-D, a true single-phase adiabatic logic family. In HSPICE simulations with post-layout extracted parasitics, our design functions correctly at frequencies exceeding 200 MHz, with total dissipation for the multiplier and BIST circuitary of 91 pJ per multiplication at 100 MHz. The chip has been fabricated in a 0.5 /spl mu/m standard CMOS process with an active area of 0.47 mm/sup 2/. Correct chip operation has been validated for operating frequencies up to 130 MHz, the limit of our experimental setup. Measured dissipation correlates well with HSPICE simulations for identical biasing conditions.