Pub Date : 2001-03-14DOI: 10.1109/ARVLSI.2001.915563
Marc H. Cohen, G. Cauwenberghs, M. Vorontsov, G. Carhart
Control of adaptive optical elements for real-time wavefront phase distortion compensation is a rapidly growing field of research and technology development. Wavefront correction is essential for reliable long distance, near-ground laser communication as well as for imaging extended objects over large distances. Crucial to adaptively correcting the wavefront is a performance metric that can be directly evaluated from the acquired image or received laser beam, to provide real-time feedback to the controller adapting the wavefront. Custom VLSI controllers and sensors are a good match to the requirements of high resolution, real-time adaptive optical systems. In this paper we introduce two VLSI focal plane sensors that supply image and beam quality metrics to an adaptive controller that performs parallel perturbative stochastic gradient descent on a spatial phase modulator in the control loop. For imaging applications, we designed an image quality metric chip that reports the high spatial frequency energy content of the received image. For laser communications applications, we designed a beam variance metric chip that calculates the compactness of the transmitted or received beam as well as its centroid location. We present experimental results from both sensor chips and demonstrate the beam variance metric chip in the feedback loop of an adaptive optics laser receiver.
{"title":"Focal-plane image and beam quality sensors for adaptive optics","authors":"Marc H. Cohen, G. Cauwenberghs, M. Vorontsov, G. Carhart","doi":"10.1109/ARVLSI.2001.915563","DOIUrl":"https://doi.org/10.1109/ARVLSI.2001.915563","url":null,"abstract":"Control of adaptive optical elements for real-time wavefront phase distortion compensation is a rapidly growing field of research and technology development. Wavefront correction is essential for reliable long distance, near-ground laser communication as well as for imaging extended objects over large distances. Crucial to adaptively correcting the wavefront is a performance metric that can be directly evaluated from the acquired image or received laser beam, to provide real-time feedback to the controller adapting the wavefront. Custom VLSI controllers and sensors are a good match to the requirements of high resolution, real-time adaptive optical systems. In this paper we introduce two VLSI focal plane sensors that supply image and beam quality metrics to an adaptive controller that performs parallel perturbative stochastic gradient descent on a spatial phase modulator in the control loop. For imaging applications, we designed an image quality metric chip that reports the high spatial frequency energy content of the received image. For laser communications applications, we designed a beam variance metric chip that calculates the compactness of the transmitted or received beam as well as its centroid location. We present experimental results from both sensor chips and demonstrate the beam variance metric chip in the feedback loop of an adaptive optics laser receiver.","PeriodicalId":424368,"journal":{"name":"Proceedings 2001 Conference on Advanced Research in VLSI. ARVLSI 2001","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128782490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-03-14DOI: 10.1109/ARVLSI.2001.915564
A. Pesavento, C. Koch
Feature detection, and tracking is a fundamental problem in computer vision research. By detecting and tracking features in an image sequence it is possible to recover information about both the motion of the viewer and the structure of the environment. The selection of features is a computationally intensive task. We derive two low-complexity algorithms that are suitable for integration in a CMOS sensor with focal-plane processing. We review the two algorithms and the circuits that implement them. We presents results from accurate simulations and experimental results from fabricated CMOS sensors.
{"title":"Methods and circuits for focal-plane computation of features in CMOS visual sensors","authors":"A. Pesavento, C. Koch","doi":"10.1109/ARVLSI.2001.915564","DOIUrl":"https://doi.org/10.1109/ARVLSI.2001.915564","url":null,"abstract":"Feature detection, and tracking is a fundamental problem in computer vision research. By detecting and tracking features in an image sequence it is possible to recover information about both the motion of the viewer and the structure of the environment. The selection of features is a computationally intensive task. We derive two low-complexity algorithms that are suitable for integration in a CMOS sensor with focal-plane processing. We review the two algorithms and the circuits that implement them. We presents results from accurate simulations and experimental results from fabricated CMOS sensors.","PeriodicalId":424368,"journal":{"name":"Proceedings 2001 Conference on Advanced Research in VLSI. ARVLSI 2001","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134331791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-03-14DOI: 10.1109/ARVLSI.2001.915559
S. Ganesan, R. Vemuri
Synthesis of mixed-signal designs from behavioral specifications must address analog-digital partitioning. In other words, determining what portions of the design are best implemented using analog and digital circuitry. In this work, we target reconfigurable mixed-signal systems composed of field-programmable analog and digital arrays. These field-programmable systems are invaluable for rapid hardware prototyping and evaluation. We begin with system behavior specified using a signal-/data-flow graph representation. This is partitioned into analog and digital domains, and then mapped onto the target mixed-signal hardware. The solution must satisfy constraints imposed by the target mixed-signal architecture on available configurable resources, available data converters, their resolution and speed, and I/O pins. The quality of the solution is evaluated based two metrics, namely feasibility and performance cost. The former is a measure of the validity of the solution with respect to the constraints. The latter measures the performance of the system based on area, bandwidth and noise.
{"title":"Analog-digital partitioning for field-programmable mixed signal systems","authors":"S. Ganesan, R. Vemuri","doi":"10.1109/ARVLSI.2001.915559","DOIUrl":"https://doi.org/10.1109/ARVLSI.2001.915559","url":null,"abstract":"Synthesis of mixed-signal designs from behavioral specifications must address analog-digital partitioning. In other words, determining what portions of the design are best implemented using analog and digital circuitry. In this work, we target reconfigurable mixed-signal systems composed of field-programmable analog and digital arrays. These field-programmable systems are invaluable for rapid hardware prototyping and evaluation. We begin with system behavior specified using a signal-/data-flow graph representation. This is partitioned into analog and digital domains, and then mapped onto the target mixed-signal hardware. The solution must satisfy constraints imposed by the target mixed-signal architecture on available configurable resources, available data converters, their resolution and speed, and I/O pins. The quality of the solution is evaluated based two metrics, namely feasibility and performance cost. The former is a measure of the validity of the solution with respect to the constraints. The latter measures the performance of the system based on area, bandwidth and noise.","PeriodicalId":424368,"journal":{"name":"Proceedings 2001 Conference on Advanced Research in VLSI. ARVLSI 2001","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131760454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-03-14DOI: 10.1109/ARVLSI.2001.915556
C. Winstead, Jie Dai, Woo Jin Kim, S. Little, Yong-Bin Kim, C. Myers, C. Schlegel
An all-MOS analog implementation of a MAP decoder is presented for the (8, 4) extended Hamming code. This paper describes the design and analysis of a tail-biting trellis decoder implementation using subthreshold CMOS devices. A VLSI test chip has recently returned from fabrication, and preliminary test results indicate accurate decoding up to 20 MBit/s.
{"title":"Analog MAP decoder for (8, 4) Hamming code in subthreshold CMOS","authors":"C. Winstead, Jie Dai, Woo Jin Kim, S. Little, Yong-Bin Kim, C. Myers, C. Schlegel","doi":"10.1109/ARVLSI.2001.915556","DOIUrl":"https://doi.org/10.1109/ARVLSI.2001.915556","url":null,"abstract":"An all-MOS analog implementation of a MAP decoder is presented for the (8, 4) extended Hamming code. This paper describes the design and analysis of a tail-biting trellis decoder implementation using subthreshold CMOS devices. A VLSI test chip has recently returned from fabrication, and preliminary test results indicate accurate decoding up to 20 MBit/s.","PeriodicalId":424368,"journal":{"name":"Proceedings 2001 Conference on Advanced Research in VLSI. ARVLSI 2001","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122502122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-03-14DOI: 10.1109/ARVLSI.2001.915553
T. Gabara
Differential signaling uses double the number of interconnects when compared to single ended signaling. The signal to interconnect usage of a differential signal is (n/2) balanced signals per n interconnects. A method is described which can increase the interconnect usage to (n-1) balanced signals per n wires. The additional bandwidth is achieved by inserting signal information into the common mode signal between two or more interconnects. Simulations in 0.251 /spl mu/m CMOS technology have indicated that bit rates of 1 Gb/s are achievable using the common mode signaling technique. These additional balanced signals can be sent in the same or opposing directions to the original information. Several schemes are described including voltage and current signaling and a bussed structure is proposed. A simple receiver structure is used to extract the common mode signal.
{"title":"Phantom mode signaling in VLSI systems","authors":"T. Gabara","doi":"10.1109/ARVLSI.2001.915553","DOIUrl":"https://doi.org/10.1109/ARVLSI.2001.915553","url":null,"abstract":"Differential signaling uses double the number of interconnects when compared to single ended signaling. The signal to interconnect usage of a differential signal is (n/2) balanced signals per n interconnects. A method is described which can increase the interconnect usage to (n-1) balanced signals per n wires. The additional bandwidth is achieved by inserting signal information into the common mode signal between two or more interconnects. Simulations in 0.251 /spl mu/m CMOS technology have indicated that bit rates of 1 Gb/s are achievable using the common mode signaling technique. These additional balanced signals can be sent in the same or opposing directions to the original information. Several schemes are described including voltage and current signaling and a bussed structure is proposed. A simple receiver structure is used to extract the common mode signal.","PeriodicalId":424368,"journal":{"name":"Proceedings 2001 Conference on Advanced Research in VLSI. ARVLSI 2001","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131834038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-03-14DOI: 10.1109/ARVLSI.2001.915560
Kip Killpack, Eric Mercer, C. Myers
This paper describes the design of a standard-cell self-timed multiplier for use in energy and area critical synchronous systems. The area of this multiplier is bounded by N rather than N/sup 2/ as seen in more traditional combinational parallel array designs, where N is the word size. Energy has a polynomial growth with word size, but has a coefficient that is much smaller than that seen in a combinational array design. Although the multiplier is self-timed, it can be embedded in a synchronous system appearing as a combinational element. This paper presents latency, area, and energy estimates for the multiplier implemented at various word sizes, and compares these numbers with a traditional combinational array multiplier. The self-timed multiplier uses 1/3 the energy and 1/7 the area of the combinational design for a 24-bit word size.
{"title":"A standard-cell self-timed multiplier for energy and area critical synchronous systems","authors":"Kip Killpack, Eric Mercer, C. Myers","doi":"10.1109/ARVLSI.2001.915560","DOIUrl":"https://doi.org/10.1109/ARVLSI.2001.915560","url":null,"abstract":"This paper describes the design of a standard-cell self-timed multiplier for use in energy and area critical synchronous systems. The area of this multiplier is bounded by N rather than N/sup 2/ as seen in more traditional combinational parallel array designs, where N is the word size. Energy has a polynomial growth with word size, but has a coefficient that is much smaller than that seen in a combinational array design. Although the multiplier is self-timed, it can be embedded in a synchronous system appearing as a combinational element. This paper presents latency, area, and energy estimates for the multiplier implemented at various word sizes, and compares these numbers with a traditional combinational array multiplier. The self-timed multiplier uses 1/3 the energy and 1/7 the area of the combinational design for a 24-bit word size.","PeriodicalId":424368,"journal":{"name":"Proceedings 2001 Conference on Advanced Research in VLSI. ARVLSI 2001","volume":"73 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120843837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-03-14DOI: 10.1109/ARVLSI.2001.915562
Sheng Sun, L. McMurchie, C. Sechen
Output Prediction Logic (OPL) is a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the restoring character of the logic family. Speedups of 2/spl times/ to 3/spl times/ over (optimized) conventional static CMOS are demonstrated for a variety of circuits, ranging from chains of gates, to datapath circuits, and to random logic benchmarks. Such speedups are obtained using identical netlists without remapping. When applied to pseudo-nMOS and dynamic families in combination with remapping to wide-input NORs, OPL yields even greater speedups over static CMOS. In this paper we present a novel 64-bit adder design implemented in OPL, using a combination of 8-bit Carry Look Ahead (CLA) and Carry Select (CS). The very fast wide-input OPL NORs enabled the use of 8-bit CLA units instead of the usual 4-bit. Using a process-independent metric for comparison, this adder is twice as fast as previously published 64-bit adders.
{"title":"A high-performance 64-bit adder implemented in output prediction logic","authors":"Sheng Sun, L. McMurchie, C. Sechen","doi":"10.1109/ARVLSI.2001.915562","DOIUrl":"https://doi.org/10.1109/ARVLSI.2001.915562","url":null,"abstract":"Output Prediction Logic (OPL) is a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the restoring character of the logic family. Speedups of 2/spl times/ to 3/spl times/ over (optimized) conventional static CMOS are demonstrated for a variety of circuits, ranging from chains of gates, to datapath circuits, and to random logic benchmarks. Such speedups are obtained using identical netlists without remapping. When applied to pseudo-nMOS and dynamic families in combination with remapping to wide-input NORs, OPL yields even greater speedups over static CMOS. In this paper we present a novel 64-bit adder design implemented in OPL, using a combination of 8-bit Carry Look Ahead (CLA) and Carry Select (CS). The very fast wide-input OPL NORs enabled the use of 8-bit CLA units instead of the usual 4-bit. Using a process-independent metric for comparison, this adder is twice as fast as previously published 64-bit adders.","PeriodicalId":424368,"journal":{"name":"Proceedings 2001 Conference on Advanced Research in VLSI. ARVLSI 2001","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126508789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-03-14DOI: 10.1109/ARVLSI.2001.915549
Suhwan Kim, C. Ziesler, M. Papaefthymiou
In this paper we present the design and experimental evaluation of an an 8-bit adiabatic multiplier with built-in self-test (BIST) logic and an internal single-phase sinusoidal power-clock generator: Both the multiplier and the BIST have been designed in SCAL-D, a true single-phase adiabatic logic family. In HSPICE simulations with post-layout extracted parasitics, our design functions correctly at frequencies exceeding 200 MHz, with total dissipation for the multiplier and BIST circuitary of 91 pJ per multiplication at 100 MHz. The chip has been fabricated in a 0.5 /spl mu/m standard CMOS process with an active area of 0.47 mm/sup 2/. Correct chip operation has been validated for operating frequencies up to 130 MHz, the limit of our experimental setup. Measured dissipation correlates well with HSPICE simulations for identical biasing conditions.
{"title":"Design, verification, and test of a true single-phase 8-bit adiabatic multiplier","authors":"Suhwan Kim, C. Ziesler, M. Papaefthymiou","doi":"10.1109/ARVLSI.2001.915549","DOIUrl":"https://doi.org/10.1109/ARVLSI.2001.915549","url":null,"abstract":"In this paper we present the design and experimental evaluation of an an 8-bit adiabatic multiplier with built-in self-test (BIST) logic and an internal single-phase sinusoidal power-clock generator: Both the multiplier and the BIST have been designed in SCAL-D, a true single-phase adiabatic logic family. In HSPICE simulations with post-layout extracted parasitics, our design functions correctly at frequencies exceeding 200 MHz, with total dissipation for the multiplier and BIST circuitary of 91 pJ per multiplication at 100 MHz. The chip has been fabricated in a 0.5 /spl mu/m standard CMOS process with an active area of 0.47 mm/sup 2/. Correct chip operation has been validated for operating frequencies up to 130 MHz, the limit of our experimental setup. Measured dissipation correlates well with HSPICE simulations for identical biasing conditions.","PeriodicalId":424368,"journal":{"name":"Proceedings 2001 Conference on Advanced Research in VLSI. ARVLSI 2001","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121067620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-03-14DOI: 10.1109/ARVLSI.2001.915546
Euiseok Kim, Jeong-Gun Lee, Dong-Ik Lee
Although there are several successful asynchronous logic synthesis tools, it is still unwieldy for designers to conceive and describe behaviors for a number of controllers constituting an asynchronous control unit of a target system manually. In this paper, building a distributed asynchronous control unit automatically through automatic derivation of hierarchically decomposed AFSMs from a CDFG is suggested. A resulting control unit consists of small asynchronous controllers and has complete separation of 'execution controllers' and 'execution order controllers'. This distributive feature leads to significant improvements in the aspects of area, performance and synthesis time of derived control circuits.
{"title":"Building a distributed asynchronous control unit through automatic derivation of hierarchically decomposed AFSMs from a CDFG","authors":"Euiseok Kim, Jeong-Gun Lee, Dong-Ik Lee","doi":"10.1109/ARVLSI.2001.915546","DOIUrl":"https://doi.org/10.1109/ARVLSI.2001.915546","url":null,"abstract":"Although there are several successful asynchronous logic synthesis tools, it is still unwieldy for designers to conceive and describe behaviors for a number of controllers constituting an asynchronous control unit of a target system manually. In this paper, building a distributed asynchronous control unit automatically through automatic derivation of hierarchically decomposed AFSMs from a CDFG is suggested. A resulting control unit consists of small asynchronous controllers and has complete separation of 'execution controllers' and 'execution order controllers'. This distributive feature leads to significant improvements in the aspects of area, performance and synthesis time of derived control circuits.","PeriodicalId":424368,"journal":{"name":"Proceedings 2001 Conference on Advanced Research in VLSI. ARVLSI 2001","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115770661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-03-14DOI: 10.1109/ARVLSI.2001.915558
V. Koosh, R. Goodman
We extend a class of analog CMOS circuits that can be used to perform many analog computational tasks. The circuits utilize MOSFETs in their subthreshold region as well as capacitors and switches to produce the computations. We show a few basic current mode building blocks that perform squaring, square root, and multiplication/division which should be sufficient to gain understanding of how to implement other power law circuits. We then combine the circuit building blocks into a more complicated circuit that normalizes a current by the square root of the sum of the squares (vector sum) of the currents. Each of these circuits have switches at the inputs of their floating gates which are used to dynamically set and restore the charges at the floating gates to proceed with the computation.
{"title":"Dynamic charge restoration of floating gate subthreshold MOS translinear circuits","authors":"V. Koosh, R. Goodman","doi":"10.1109/ARVLSI.2001.915558","DOIUrl":"https://doi.org/10.1109/ARVLSI.2001.915558","url":null,"abstract":"We extend a class of analog CMOS circuits that can be used to perform many analog computational tasks. The circuits utilize MOSFETs in their subthreshold region as well as capacitors and switches to produce the computations. We show a few basic current mode building blocks that perform squaring, square root, and multiplication/division which should be sufficient to gain understanding of how to implement other power law circuits. We then combine the circuit building blocks into a more complicated circuit that normalizes a current by the square root of the sum of the squares (vector sum) of the currents. Each of these circuits have switches at the inputs of their floating gates which are used to dynamically set and restore the charges at the floating gates to proceed with the computation.","PeriodicalId":424368,"journal":{"name":"Proceedings 2001 Conference on Advanced Research in VLSI. ARVLSI 2001","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133483485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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