{"title":"Versatile chip-level integrated test vehicle for dynamic thermal evaluation","authors":"Suresh Parameswaran, S. Balakrishnan, Boon Ang","doi":"10.1109/ICMTS.2018.8383779","DOIUrl":null,"url":null,"abstract":"Thermal management of semiconductor chips is becoming very important as the demand for chip performance increases. It is necessary to evaluate/manage the thermal aspects of a chip throughout the development cycle — starting from initial planning stage to deployment on customer board and beyond. In this paper, we present a versatile thermal evaluation vehicle that addresses the above requirements. This paper describes the circuit architecture/implementation, details of operation, programming aspects, usage model and various applications of a silicon chip that is successfully used as a thermal evaluation tool. The chip has 1600 sectors with programmable heat-generation and temperature-sensing capability — enabling it to generate up to 3W per mm2 and has a temperature detection range of 30C to 125C with an accuracy of +/−2C. It has a simple implementation and is easy to program and test — yet has substantial thermal evaluation capabilities. It was fabricated in 0.18um technology and packaged as flip-chip. The chip has ability to do automated on-chip temperature measurements through a tester-friendly interface and has been successfully controlled through a simple and inexpensive test-platform. The ability to generate heat on-die and monitor spatial & temporal on-die temperature makes this chip suitable to emulate many different use cases of a product during the development stage ahead of product silicon availability. The capabilities of this test-vehicle make it a suitable candidate for demonstrating power-aware/thermal-aware testing. Silicon measurement data and comparison to simulation results based on numerical models are also presented in this paper.","PeriodicalId":271839,"journal":{"name":"2018 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Conference on Microelectronic Test Structures (ICMTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMTS.2018.8383779","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Thermal management of semiconductor chips is becoming very important as the demand for chip performance increases. It is necessary to evaluate/manage the thermal aspects of a chip throughout the development cycle — starting from initial planning stage to deployment on customer board and beyond. In this paper, we present a versatile thermal evaluation vehicle that addresses the above requirements. This paper describes the circuit architecture/implementation, details of operation, programming aspects, usage model and various applications of a silicon chip that is successfully used as a thermal evaluation tool. The chip has 1600 sectors with programmable heat-generation and temperature-sensing capability — enabling it to generate up to 3W per mm2 and has a temperature detection range of 30C to 125C with an accuracy of +/−2C. It has a simple implementation and is easy to program and test — yet has substantial thermal evaluation capabilities. It was fabricated in 0.18um technology and packaged as flip-chip. The chip has ability to do automated on-chip temperature measurements through a tester-friendly interface and has been successfully controlled through a simple and inexpensive test-platform. The ability to generate heat on-die and monitor spatial & temporal on-die temperature makes this chip suitable to emulate many different use cases of a product during the development stage ahead of product silicon availability. The capabilities of this test-vehicle make it a suitable candidate for demonstrating power-aware/thermal-aware testing. Silicon measurement data and comparison to simulation results based on numerical models are also presented in this paper.