A 68ns 4Mbit CMOS EPROM with high noise immunity design

Symposium 1989 on VLSI Circuits Pub Date : 1989-05-25 DOI:10.1109/VLSIC.1989.1037478

K. Imamiya, J. Miyamoto, N. Ohtstika, S. Atsurni, T. Sako, Y. Muroya, S. Mori, K. Yoshikawa, S. Tanaka

引用次数: 5

Abstract

In a VLSI memory, noise generated by its own operation becomes a serious problem. The noise disturbs data sensing, especially in EPROM's which have a single-ended sensing scheme. To develop high- density and high-speed EPROM's, it is inevitably necessary to solve the noise problems. Incorrect EPROM functions due to the noise are dis- cussed in this paper. High-noise-immunity circuit techniques are proposed for stable data sensing and high-speed access time. Thesecare divided bit-line layout, reference line with dummy bit lines, and CE transition detector. Using these circuit techniques and 0.8- pm n-well CMOS technol- ogy, a 512K X 8-bit CMOS EPROM was developed. A 6&ns access time was achieved. The die sue is 5.62 mm X 15.30 mm and it is assembled in a 600-mil cerdip package.

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具有高抗噪设计的68ns 4Mbit CMOS EPROM

在超大规模集成电路存储器中，其自身运行产生的噪声成为一个严重的问题。噪声干扰了数据传感，特别是在单端传感方案的EPROM中。要发展高密度、高速的EPROM，必然要解决噪声问题。本文讨论了噪声对EPROM功能的影响。为了稳定的数据感知和高速的访问时间，提出了高抗噪电路技术。它们包括分割位线布局、带虚拟位线的参考线和CE过渡检测器。利用这些电路技术和0.8 pm n阱CMOS技术，开发了一个512K X 8位CMOS EPROM。实现了6&ns的访问时间。该模具是5.62毫米X 15.30毫米，它是在一个600毫米的cerdip封装组装。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Symposium 1989 on VLSI Circuits

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