Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037523
T. Yaguchi, K. Fujimoto, E. Katsumata, K. Tanaka, K. Tamaru, A. Kanuma, Y. Katagiri, A. Nishikawa, H. Shiraishi, T. Yamamoto, K. Kimura, Y. Terui, T. Hamai
{"title":"Design of a CMOS token ring LAN controller, TRC, compatible with IEEE802.5 MAC protocol","authors":"T. Yaguchi, K. Fujimoto, E. Katsumata, K. Tanaka, K. Tamaru, A. Kanuma, Y. Katagiri, A. Nishikawa, H. Shiraishi, T. Yamamoto, K. Kimura, Y. Terui, T. Hamai","doi":"10.1109/VLSIC.1989.1037523","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037523","url":null,"abstract":"","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125533437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037510
J. Okamura, Y. Okada, M. Koyanagi, Y. Takeuchi, M. Yamada, K. Sakurai, S. Imada, S. Saito
The decoded-source sense amplifier (DSSA) for high-speed, high-density DRAMs is discussed. To prevent clamping of the common-source node of the sense amplifier caused by bit-line discharge current, the DSSA has an additional latching transistor with a gate controlled by a column decoder. The DSSA has been successfully installed in a 4-Mb DRAM and provided a RAS access time of 60 ns under a V/sub cc/ of 4 V at 85 degrees C. >
{"title":"Decoded-source sense amplifier for high-density DRAMs","authors":"J. Okamura, Y. Okada, M. Koyanagi, Y. Takeuchi, M. Yamada, K. Sakurai, S. Imada, S. Saito","doi":"10.1109/VLSIC.1989.1037510","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037510","url":null,"abstract":"The decoded-source sense amplifier (DSSA) for high-speed, high-density DRAMs is discussed. To prevent clamping of the common-source node of the sense amplifier caused by bit-line discharge current, the DSSA has an additional latching transistor with a gate controlled by a column decoder. The DSSA has been successfully installed in a 4-Mb DRAM and provided a RAS access time of 60 ns under a V/sub cc/ of 4 V at 85 degrees C. >","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122393713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037518
E. Kowashi, T. Uchimura, K. Neki, H. Hasegawa
This paper presents a binary image data compression and expansion processor that can compress 500 kbytes of image data into 35 kbyles of code data in 0.41 seconds. The pmessor equips with dala flow hardwax and CPU on the one chip. Topics described include the algorithms, anhifp.ture. and perfnmance. Visua-interface belween man and machine is of peat concern today. A large amount of imagc data has to he handled efficiently to imprwe this interface. For cxamplc, when an A4-sirc page of image is scanned at density of 200 pixelginch. the resultant image dam amouns to 500 kbyles. It takes so long as 7 minutes to !"fer this by 9,600 bps MODEM. If requires one diskette to store this on a 2DD 3.5 inch floppy. In order to improve the efficiency, several coding schemes of compressing binary image data were recommended by the CCI'IT' 2. By applying one of the recommended methods, one page of image data can be compressed into 1/14. 35 kbytes of code data (Figure 1). Then one page of image can be transferred within 30 seconds. Thirteen pages of image can be stored on a floppy diskette. But another problem here is that it takes about 15 seconds for a multi-purpose processor to compress one page of image dab.
本文介绍了一种二进制图像数据压缩扩展处理器，可以在0.41秒内将500kb的图像数据压缩为35kb的代码数据。该传感器在一个芯片上配备了数据流硬件和CPU。所描述的主题包括算法，非hihipture。和perfnmance。人机界面是当今社会关注的热点问题。为了改进这个界面，需要对大量的图像数据进行有效的处理。例如，当以200像素的密度扫描A4-sirc页图像时。由此形成的图像坝高达500千米。通过9600 bps的MODEM发送此消息需要7分钟。它需要一个软盘来将其存储在2DD 3.5英寸软盘上。为了提高压缩效率，CCI' it ' 2推荐了几种压缩二值图像数据的编码方案。通过应用其中一种推荐的方法，可以将一页图像数据压缩到1/14。35 kb的代码数据(图1)，那么30秒内可以传输一页图像。一张软盘可以存储13页图像。但这里的另一个问题是，多用途处理器压缩一页图像需要大约15秒。
{"title":"A data flow image compression processor","authors":"E. Kowashi, T. Uchimura, K. Neki, H. Hasegawa","doi":"10.1109/VLSIC.1989.1037518","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037518","url":null,"abstract":"This paper presents a binary image data compression and expansion processor that can compress 500 kbytes of image data into 35 kbyles of code data in 0.41 seconds. The pmessor equips with dala flow hardwax and CPU on the one chip. Topics described include the algorithms, anhifp.ture. and perfnmance. Visua-interface belween man and machine is of peat concern today. A large amount of imagc data has to he handled efficiently to imprwe this interface. For cxamplc, when an A4-sirc page of image is scanned at density of 200 pixelginch. the resultant image dam amouns to 500 kbyles. It takes so long as 7 minutes to !\"fer this by 9,600 bps MODEM. If requires one diskette to store this on a 2DD 3.5 inch floppy. In order to improve the efficiency, several coding schemes of compressing binary image data were recommended by the CCI'IT' 2. By applying one of the recommended methods, one page of image data can be compressed into 1/14. 35 kbytes of code data (Figure 1). Then one page of image can be transferred within 30 seconds. Thirteen pages of image can be stored on a floppy diskette. But another problem here is that it takes about 15 seconds for a multi-purpose processor to compress one page of image dab.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122927106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037466
Y. Nakakura, K. M. Sameky, Y. Tue, I. Okabayashi, M. Nakajima, S. Karino, K. Kaneko, H. Kadota
1. Intrdudirm VLSl parallel pmwssor system Is one of pmmlslng candldates for the future machine to carry out heavy-duty numerlcal computation. For the parallel system. not only PElprocessor element) operation speed but also Inter-PE data transfer Is very Important to achleve high performance. Especially. in the parallel processor system with localized memories and a connection network. there are two malor questions : "haw to realize emcient data transfer between local memories wlth mlnlmum lnterference wlth PE operatlons." and "how to assign the data In local memories? A new VLSI controller has been dmloped as a versatile data-transfcr control unR, X U , In a hlgh-prrfmmancc parallel pmccsor system : ADENAUI. The chtp gives some answers to the questions by the hardware. In this paper. the archltecture and the operations of TCU and the circults far the dedicated addrwslng block Address Generator are cxplalned. The chlp layout techniques are also discussed.
{"title":"A versatile data-transfer control unit for a parallel processor system","authors":"Y. Nakakura, K. M. Sameky, Y. Tue, I. Okabayashi, M. Nakajima, S. Karino, K. Kaneko, H. Kadota","doi":"10.1109/VLSIC.1989.1037466","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037466","url":null,"abstract":"1. Intrdudirm VLSl parallel pmwssor system Is one of pmmlslng candldates for the future machine to carry out heavy-duty numerlcal computation. For the parallel system. not only PElprocessor element) operation speed but also Inter-PE data transfer Is very Important to achleve high performance. Especially. in the parallel processor system with localized memories and a connection network. there are two malor questions : \"haw to realize emcient data transfer between local memories wlth mlnlmum lnterference wlth PE operatlons.\" and \"how to assign the data In local memories? A new VLSI controller has been dmloped as a versatile data-transfcr control unR, X U , In a hlgh-prrfmmancc parallel pmccsor system : ADENAUI. The chtp gives some answers to the questions by the hardware. In this paper. the archltecture and the operations of TCU and the circults far the dedicated addrwslng block Address Generator are cxplalned. The chlp layout techniques are also discussed.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130555288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037464
M. Usami, N. Shiozawa
In this contribution we would like to present a nev bipolar low -power high -speed logic circuit named SPL (Super Push-pull Logic). At a low P O Y ~ ~ per gate range of lnu/gste, the calculated path propagation delay time of SPL gates loading wire capacitances of 0.57pF/gate is 2.75 times faster than the one of conventional ECL(Enitter Coupled Logic) gates. INTRODUCTION The performance of high-speed bipolar gate arrays using ECL circuit technology is usually limited by LSI power dissipation. Lor-power NTL (Non -Threshold Logic) (1) ( 2 ) circuit has been developed for the bipolar high-packing density LSI's. In Hitachi. 5000-gate NTL gate arrays have been applied for supercomputer S-820 and large -scaled commercial computers (3) . High performance of NTL circuit is obtained by a linear amplifier like operation and a speed-up capacitance(Fig.1). But the driving capability of loading capacitances of the NTL circuits still depends on the output emitter follower current level, mhich is the reason not to decrease the power dissipation. SPL's design concept is based on how to overcome this NTL weak point. CIRCUIT CONCEPT AND OPERATION Table 1 summarizes the characteristics of SPL circuit. SPL has outstanding driving capability of 0.1311s / PF at law gate power compared rith the other circuit types as shorn in Fig.2. This merit of SPL is obtained by an AC coupled active push-pull circuit driven by the NTL inherent input inverter transistor, To improve the impulse response time, the base terminal of the output pull-doun transistor is biased by the low impedance emitter of the additonal clamp transistor. Fig.3 shovs the simulation data of the output voltage waveforms and the transient current waveforms in order to charge and discharge the heavy loading capacitances of 3pF. To keep the driving capability and save the power dissipation, a coupling capacitance C1 i n SPL has better be changed according to the loading capacitance CL. The pull-down transistor shortly turns off to be high impedance state, which enables output vired OR function features. PATH DELAY SIMULATION To show the high-speed operation of SPL. the tentative logic path propagation delay time r e s simulated as shown in Fig.5. The logic path of conventional IO-stage ECL gates including wired AND (collector dotting) and wired OR (emitter dotting) functions is converted to the one of equivalent 15-stage SPL gates. A single ECL wired AND gate is equal to double SPL NOR gates in tandem. In spite of this handicap, the path delay of SPL keeps advantage against the one of ECL on the condition of average loading wire capacitances of 0.57pF/gate. At the low power level of l m / g a t e , SPL shows high speed path delay of 3.3ns, which improves ECL gate delay of 9.1"s by a factor of 2.75. Moreover, these SPL features sill be enhanced according to the transistor parameter progress especially of ft, Cte and rbb'. SPL rill be a brakthrough force of developing highpacking density and high-speed LSI's. APPL
{"title":"SPL (super push-pull logic) a bipolar novel low-power high-speed logic circuit","authors":"M. Usami, N. Shiozawa","doi":"10.1109/VLSIC.1989.1037464","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037464","url":null,"abstract":"In this contribution we would like to present a nev bipolar low -power high -speed logic circuit named SPL (Super Push-pull Logic). At a low P O Y ~ ~ per gate range of lnu/gste, the calculated path propagation delay time of SPL gates loading wire capacitances of 0.57pF/gate is 2.75 times faster than the one of conventional ECL(Enitter Coupled Logic) gates. INTRODUCTION The performance of high-speed bipolar gate arrays using ECL circuit technology is usually limited by LSI power dissipation. Lor-power NTL (Non -Threshold Logic) (1) ( 2 ) circuit has been developed for the bipolar high-packing density LSI's. In Hitachi. 5000-gate NTL gate arrays have been applied for supercomputer S-820 and large -scaled commercial computers (3) . High performance of NTL circuit is obtained by a linear amplifier like operation and a speed-up capacitance(Fig.1). But the driving capability of loading capacitances of the NTL circuits still depends on the output emitter follower current level, mhich is the reason not to decrease the power dissipation. SPL's design concept is based on how to overcome this NTL weak point. CIRCUIT CONCEPT AND OPERATION Table 1 summarizes the characteristics of SPL circuit. SPL has outstanding driving capability of 0.1311s / PF at law gate power compared rith the other circuit types as shorn in Fig.2. This merit of SPL is obtained by an AC coupled active push-pull circuit driven by the NTL inherent input inverter transistor, To improve the impulse response time, the base terminal of the output pull-doun transistor is biased by the low impedance emitter of the additonal clamp transistor. Fig.3 shovs the simulation data of the output voltage waveforms and the transient current waveforms in order to charge and discharge the heavy loading capacitances of 3pF. To keep the driving capability and save the power dissipation, a coupling capacitance C1 i n SPL has better be changed according to the loading capacitance CL. The pull-down transistor shortly turns off to be high impedance state, which enables output vired OR function features. PATH DELAY SIMULATION To show the high-speed operation of SPL. the tentative logic path propagation delay time r e s simulated as shown in Fig.5. The logic path of conventional IO-stage ECL gates including wired AND (collector dotting) and wired OR (emitter dotting) functions is converted to the one of equivalent 15-stage SPL gates. A single ECL wired AND gate is equal to double SPL NOR gates in tandem. In spite of this handicap, the path delay of SPL keeps advantage against the one of ECL on the condition of average loading wire capacitances of 0.57pF/gate. At the low power level of l m / g a t e , SPL shows high speed path delay of 3.3ns, which improves ECL gate delay of 9.1\"s by a factor of 2.75. Moreover, these SPL features sill be enhanced according to the transistor parameter progress especially of ft, Cte and rbb'. SPL rill be a brakthrough force of developing highpacking density and high-speed LSI's. APPL","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127042766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037474
S. Hayakawa, M. Kakumu, A. Aono, T. Yoshida, K. Sato, K. Noguchu, T. Ohtani, T. Nakayama, T. Asami, S. Morita, M. Kinugawa, J. Matsunaga, K. Ochit
1. Inboduetiao A 13- 1Mb CMOS SRAM fabricated with uipk polysilicon, double metal layers and 0.5~ gate MOS FET's will be described. The RAM utilizes the divided double-word-line scheme and three stage sense ampli6ers for high-speed operation. MMWV~L performance of the RAM is enhanced by 0.5~ MOS devices fully used in the internal circuits. An on-chip voltage down converter ( VDC ) is well designed to supply the inled VCC of 3.3V and to maintain lhe nliability of 0.5~ devices at external 5V operation.
{"title":"High-reliability and high-speed design of 1Mb CMOS SRAM with 0.5/spl mu/m devices","authors":"S. Hayakawa, M. Kakumu, A. Aono, T. Yoshida, K. Sato, K. Noguchu, T. Ohtani, T. Nakayama, T. Asami, S. Morita, M. Kinugawa, J. Matsunaga, K. Ochit","doi":"10.1109/VLSIC.1989.1037474","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037474","url":null,"abstract":"1. Inboduetiao A 13- 1Mb CMOS SRAM fabricated with uipk polysilicon, double metal layers and 0.5~ gate MOS FET's will be described. The RAM utilizes the divided double-word-line scheme and three stage sense ampli6ers for high-speed operation. MMWV~L performance of the RAM is enhanced by 0.5~ MOS devices fully used in the internal circuits. An on-chip voltage down converter ( VDC ) is well designed to supply the inled VCC of 3.3V and to maintain lhe nliability of 0.5~ devices at external 5V operation.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121640661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037487
R. Hester, K. Tan, M. De Wit, J. Fattaruso, S. Kiriaki, F. Tsay, Ç. Kaya, J. Paterson, H. Tigelaar
One of the sources of non-linearity in charge-redistribution analog-to-digital converters (ADCs) is capacitor voltage dependence. This paper will discuss Circuit techniques l o eliminate conversion errors caused by the capacitor voltage dependence, and performance data from circuits realized in a linear CMOS process will be presented. bv Cawsilor Voltaoe DBoendence The dependence of capacitance on voltage can be expressed by (1) where V represents the potential differsnce between the capacitor plates 111. Depending upon the capacitor plate and dielectric materials and the dielectric thickness, the linear coefficient. CI, can vary from 10s to 100s parts per million per volt. The quadratic coefficient, Cp, is typically much smaller. rarely exceeding 10 ppmlvolt2. The schematic diagram of a single-ended chargeredistribution capacitor array is shown in Figure 1. Its operation accomplishes both the sample-and-hold and successive approximation functions. When sampling the analog input signal, the top plate common to all capacitors is charged to VRS while the bottom plates are charged to VIN. When the sampling switches open, successive approximation Is executed connecting the bottom plates of the capacitors to either of two ievels. usually a reference voltage VREF and ground. Upon completion. the common lop piate node will return to VRS. It can be shown that the conversion error caused by capacitor voltage dependence can be expressed as c = CO I1 + c,v + C2V2), ~ ~ l N ~ ~ v l N ~ v R E F ~ ~ c l 12+C2VRS +[VIN+VREFl[%/31). (2) Typically, CMOS ADCs up lo 10-bit resolution are implemented in the single-ended topology of Figure 1. and voltage coefficients up l o 800 ppmlvolt can be tolerated. Beyond IO-bit resolution, fully-differential topologies are used. This architecture provides substantial improvements in noise immunity as well as an important extra degree of freedom in the sample-and-hold operation that is exploited in this work. The fully-differential architecture is composed of two identical capacitor arrays. During sampling, the top plates of bcth arrays are charged to VsAM, while the bottom plates of one array are charged lo VIN+ and those of the other array are charged to VIN~. During successive approximation, the bottom plates are connected either to VREF or ground as in the single ended case. When a particular capacitor in one array is connected to VREF. the corresponding capacitor in the other array is connected to ground. Completion of conversion leaves both top plates at potential, VT. The error of the fullydifferential ~ t r ~ ~ t ~ l e can be expressed by (c1 VINO/z) (2VT-VREF+(VSAM-V,,+)2.(vSAM~vlN~)z) + (31 +(CZVIND/3) (vT3-(vT-vREF)3 +(VSAM-VIN+)3-(vSAM-VlN-)3) 3 where VINO = VIN+ VI,.. Linear V . . The term involving C1 vanishes when the sampling and successive approximation are executed such that ZVT = V w andVW = (VIN++VIN.)12. In this case, equation (3) reduces to Figure 2 shows a schematic diagram of a circuit accomplishing this
电容电压依赖性是电荷再分配模数转换器(adc)非线性的来源之一。本文将讨论电路技术，以消除由电容器电压依赖引起的转换误差，并将介绍在线性CMOS工艺中实现的电路的性能数据。电容对电压的依赖关系可以用式(1)表示，其中V表示电容器极板之间的电位差。根据电容器极板和介电材料以及介电厚度的不同，其线性系数也不同。CI的变化范围从百万分之10到百万分之100。二次系数Cp通常要小得多。很少超过10毫伏。单端电荷分布电容器阵列的原理图如图1所示。它的操作既实现了抽样保持函数，也实现了逐次逼近函数。当采样模拟输入信号时，所有电容器共有的顶板充电到VRS，而底板充电到VIN。当采样开关打开时，将电容器的底板连接到两个电平中的任意一个进行逐次逼近。通常是参考电压VREF和地。在完成。共同的lop节点将返回到VRS。由电容电压依赖性引起的转换误差可以表示为c = CO I1 + c,v + C2V2)， ~ ~ 1 N ~ ~ v l N ~ v REF ~ ~ c l 12+C2VRS +[VIN+VREFl] %/31。(2)通常情况下，CMOS adc在图1的单端拓扑结构中实现低10位分辨率。电压系数可达1 ~ 800ppmlv。除了io位分辨率之外，还使用了全差分拓扑。这种结构在噪声抗扰性方面提供了实质性的改进，并且在本工作中利用的采样保持操作中提供了重要的额外自由度。全差分架构由两个相同的电容阵列组成。采样时，两个阵列的顶板都带电到VsAM，一个阵列的底板都带电到VIN+，另一个阵列的底板都带电到VIN~。在逐次逼近时，底板连接到VREF或接地，就像单端情况一样。当一个阵列中的特定电容器连接到VREF时。另一阵列对应的电容接地。转换完成后，两个顶板在电位VT处。全微分~ t ~ r ~ t ~ le的误差可以表示为(c1 VINO/z) (2VT-VREF+(vSAM- v，，+)2.(vSAM~vlN~)z) +(31 +(CZVIND/3) (vT3-(VT- vref)3 +(vSAM- VIN+)3-(vSAM- vlN -)3) 3，其中VINO = VIN+ VI，…线性V。当执行抽样和逐次逼近使ZVT = vw和vw = (v++ VIN.)时，涉及C1的项消失。在这种情况下，公式(3)简化为图2所示的电路原理图。电阻分压器用于从差分输入导出共模输入信号。在采样期间，两个阵列的顶板都被充电到这个共模电压。导致VINoR出现在上部数组中，-VIND/~出现在下部数组中。图中所示是一个可选的单位增益缓冲器，当采样速度很重要时可以使用。当所有开关(Ok)关闭并且MSB(符号位)确定时，开始逐次逼近。请注意，ON和lN (MSB)开关连接到V R ~ ~和接地总线的方式与所有其他Ok和l k开关不同。这允许双极输入信号，并将V， #共模信号添加到分接板。这个共模电平在转换期间保持不变，使VT=VREF/2保持所需值。除了消去线性电压系数。这种采样方法的另一个重要优点是提供给比较器的共模电压与输入共模电压保持独立。这放宽了比较器的共模抑制要求。图3显示了WO aoc的模拟误差函数。它们的区别只是信号的采样方式不同。其中，VSIYII=VREF/2。另一个VsAM=(v++ vIN .)/2。模拟中使用的电压系数与图4中用于制造ADC的电容器相对应。图4显示了采用这种采样技术的实验性13位转换器的误差函数。图3中V,O= -VREF处的严重误差在图4中明显不存在。(c2/1 2) (vIND) (vREFz。(4) . (1) . (4) . (1) . (3) . (1) . (3) . (1) . (1) . (3) . (1) . (1) . (1) . (1) . (1) . (1) . (1) . (1) . (1) . (1) .)转换器线性度可达15位。大于15bit的线性度需要二次电压系数校正。这是通过添加一个信号来实现的。到采样期间的输入。变量。G.是一种可调增益因子，允许在C2值范围内进行补偿。 执行校准算法以确定gl的最优值，以消除式(4)中给出的误差信号。实现这种校正所需的硬件包括附加在主电容器阵列顶板上的单独校正电容器阵列。非线性函数发生器，以及用于存储G值和控制校正阵列的数字寄存器。当对输入信号进行采样时，函数发生器产生一个与vl N O (V ~ ~ ~ z V ~ ~ ~ 2)成比例的信号，该信号被采样到特殊阵列的一小部分上。分数由G寄存器决定。后取样。在逐次逼近过程中，这种特殊阵列的极板连接到VRE~IP，有效地成为寄生电容。结果是少量的电荷被添加到信号电荷中
{"title":"Analog-to-digital converter with non-linear capacitor compensation","authors":"R. Hester, K. Tan, M. De Wit, J. Fattaruso, S. Kiriaki, F. Tsay, Ç. Kaya, J. Paterson, H. Tigelaar","doi":"10.1109/VLSIC.1989.1037487","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037487","url":null,"abstract":"One of the sources of non-linearity in charge-redistribution analog-to-digital converters (ADCs) is capacitor voltage dependence. This paper will discuss Circuit techniques l o eliminate conversion errors caused by the capacitor voltage dependence, and performance data from circuits realized in a linear CMOS process will be presented. bv Cawsilor Voltaoe DBoendence The dependence of capacitance on voltage can be expressed by (1) where V represents the potential differsnce between the capacitor plates 111. Depending upon the capacitor plate and dielectric materials and the dielectric thickness, the linear coefficient. CI, can vary from 10s to 100s parts per million per volt. The quadratic coefficient, Cp, is typically much smaller. rarely exceeding 10 ppmlvolt2. The schematic diagram of a single-ended chargeredistribution capacitor array is shown in Figure 1. Its operation accomplishes both the sample-and-hold and successive approximation functions. When sampling the analog input signal, the top plate common to all capacitors is charged to VRS while the bottom plates are charged to VIN. When the sampling switches open, successive approximation Is executed connecting the bottom plates of the capacitors to either of two ievels. usually a reference voltage VREF and ground. Upon completion. the common lop piate node will return to VRS. It can be shown that the conversion error caused by capacitor voltage dependence can be expressed as c = CO I1 + c,v + C2V2), ~ ~ l N ~ ~ v l N ~ v R E F ~ ~ c l 12+C2VRS +[VIN+VREFl[%/31). (2) Typically, CMOS ADCs up lo 10-bit resolution are implemented in the single-ended topology of Figure 1. and voltage coefficients up l o 800 ppmlvolt can be tolerated. Beyond IO-bit resolution, fully-differential topologies are used. This architecture provides substantial improvements in noise immunity as well as an important extra degree of freedom in the sample-and-hold operation that is exploited in this work. The fully-differential architecture is composed of two identical capacitor arrays. During sampling, the top plates of bcth arrays are charged to VsAM, while the bottom plates of one array are charged lo VIN+ and those of the other array are charged to VIN~. During successive approximation, the bottom plates are connected either to VREF or ground as in the single ended case. When a particular capacitor in one array is connected to VREF. the corresponding capacitor in the other array is connected to ground. Completion of conversion leaves both top plates at potential, VT. The error of the fullydifferential ~ t r ~ ~ t ~ l e can be expressed by (c1 VINO/z) (2VT-VREF+(VSAM-V,,+)2.(vSAM~vlN~)z) + (31 +(CZVIND/3) (vT3-(vT-vREF)3 +(VSAM-VIN+)3-(vSAM-VlN-)3) 3 where VINO = VIN+ VI,.. Linear V . . The term involving C1 vanishes when the sampling and successive approximation are executed such that ZVT = V w andVW = (VIN++VIN.)12. In this case, equation (3) reduces to Figure 2 shows a schematic diagram of a circuit accomplishing this","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130947061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037497
F. Miyaji, T. Emort, Y. Matsuyama, Y. Kanaishi, K. Senoh, Y. Hagiwara
In recent years, the memory bit density of SRAM's becomes higher and higher. On the other hand, the testing time which is composed of DC parametric and AC functional tests becomes longer and longer. The AC test time increases in proportion to the memory bit density vhen N-test patterns are used. Therefore, the testing time of 4Mb SRAM is quadruple compared with that of 1Mb SRAM's in the case of the same bit organizations. It is very serious problem to spend long testing time in mass production. Therefore, the test modes for reduction of the testing time have been developed 111-[3l. But Multi Bit Test (MET) trigger circuit for SRAM's has not been developed in the case of the no extra NC (Non Connection)pin package. This paper will present a MBT trigger circuit for Mbit SRAH's having no extra NC pin package.
{"title":"A multi bit test trigger circuit for Mbit SRAM's","authors":"F. Miyaji, T. Emort, Y. Matsuyama, Y. Kanaishi, K. Senoh, Y. Hagiwara","doi":"10.1109/VLSIC.1989.1037497","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037497","url":null,"abstract":"In recent years, the memory bit density of SRAM's becomes higher and higher. On the other hand, the testing time which is composed of DC parametric and AC functional tests becomes longer and longer. The AC test time increases in proportion to the memory bit density vhen N-test patterns are used. Therefore, the testing time of 4Mb SRAM is quadruple compared with that of 1Mb SRAM's in the case of the same bit organizations. It is very serious problem to spend long testing time in mass production. Therefore, the test modes for reduction of the testing time have been developed 111-[3l. But Multi Bit Test (MET) trigger circuit for SRAM's has not been developed in the case of the no extra NC (Non Connection)pin package. This paper will present a MBT trigger circuit for Mbit SRAH's having no extra NC pin package.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127634733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037505
Y. Sugimoto, S. Mizoguchi, T. Matsuyama, J. Sano, H. Nakayama, M. Taguchi
{"title":"A TV(UHF/VHF)/Fm/AM compatible Bi-CMOS 1GHz single chip PLL IC","authors":"Y. Sugimoto, S. Mizoguchi, T. Matsuyama, J. Sano, H. Nakayama, M. Taguchi","doi":"10.1109/VLSIC.1989.1037505","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037505","url":null,"abstract":"","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117346163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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