A Lightweight Reconfigurable RRAM-based PUF for Highly Secure Applications

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2020-10-19 DOI:10.1109/DFT50435.2020.9250829

Basma Hajri, Mohammad M. Mansour, A. Chehab, H. Aziza

{"title":"A Lightweight Reconfigurable RRAM-based PUF for Highly Secure Applications","authors":"Basma Hajri, Mohammad M. Mansour, A. Chehab, H. Aziza","doi":"10.1109/DFT50435.2020.9250829","DOIUrl":null,"url":null,"abstract":"Recently, the variability of resistive memory devices (RRAM) has become an attractive feature for hardware security in the form of a Physically Unclonable Function (PUF). Although several RRAM-based PUFs have appeared in the literature, they still suffer from some issues related to reliability, reconfigurability, and extensive integration cost. This paper presents a novel lightweight reconfigurable RRAM-based PUF (LRR-PUF) wherein multiple RRAM cells, connected to the same bit line and same transistor (1T4R), are used to generate a single bit response. The pulse programming method used is also innovative and exploits variations in the number of pulses needed to switch the RRAM cell as the primary entropy source of the PUF. The main feature of the proposed PUF is its integration with any RRAM architecture at almost no additional cost. Through extensive simulations, including the impact of temperature and voltage variations along with statistical characterization, we demonstrate that the LRR-PUF exhibits such attractive properties including high reliability (almost 100%), reconfigurability, uniqueness, cost, and efficiency.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"273 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFT50435.2020.9250829","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

Abstract

Recently, the variability of resistive memory devices (RRAM) has become an attractive feature for hardware security in the form of a Physically Unclonable Function (PUF). Although several RRAM-based PUFs have appeared in the literature, they still suffer from some issues related to reliability, reconfigurability, and extensive integration cost. This paper presents a novel lightweight reconfigurable RRAM-based PUF (LRR-PUF) wherein multiple RRAM cells, connected to the same bit line and same transistor (1T4R), are used to generate a single bit response. The pulse programming method used is also innovative and exploits variations in the number of pulses needed to switch the RRAM cell as the primary entropy source of the PUF. The main feature of the proposed PUF is its integration with any RRAM architecture at almost no additional cost. Through extensive simulations, including the impact of temperature and voltage variations along with statistical characterization, we demonstrate that the LRR-PUF exhibits such attractive properties including high reliability (almost 100%), reconfigurability, uniqueness, cost, and efficiency.

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

用于高度安全应用的轻量级可重构随机存储器PUF

最近，电阻性存储器件(RRAM)的可变性以物理不可克隆功能(PUF)的形式成为硬件安全的一个有吸引力的特征。尽管文献中已经出现了几种基于ram的puf，但它们仍然存在一些与可靠性、可重构性和大量集成成本相关的问题。本文提出了一种新型的轻量级可重构RRAM PUF (LRR-PUF)，其中多个RRAM单元连接到相同的位线和相同的晶体管(1T4R)，用于产生单个位响应。所使用的脉冲编程方法也是创新的，它利用切换RRAM单元所需的脉冲数量的变化作为PUF的主要熵源。所提出的PUF的主要特点是它与任何RRAM架构的集成几乎没有额外的成本。通过广泛的模拟，包括温度和电压变化的影响以及统计特性，我们证明了LRR-PUF具有高可靠性(几乎100%)、可重构性、唯一性、成本和效率等吸引人的特性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文去求助

来源期刊

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

自引率

0.00%

发文量

期刊最新文献

Variation-Aware Test for Logic Interconnects using Neural Networks – A Case Study A Pipelined Multi-Level Fault Injector for Deep Neural Networks Reliable Classification with Ensemble Convolutional Neural Networks Hardware Accelerator Design with Supervised Machine Learning for Solar Particle Event Prediction Latest Trends in Hardware Security and Privacy