Pub Date : 2020-10-19DOI: 10.1109/DFT50435.2020.9250888
G. Chapman, Rohan Thomas, Klinsmann J. Coelho Silva Meneses, Ruoyi Zhao, I. Koren, Z. Koren
Camera Integrated circuits (ICs) suffer from soft errors known as Single Event Upsets (SEUs). Unlike traditional ICs, camera sensors record the location and energy deposited by each SEU. Camera pixels measure when and where cosmic ray particles hit and store the deposited charge when dark-frame images are taken. Hence, with large datasets of time-lapsed dark-frame images, pixel analysis provides the intensity and energy distribution of deposited SEU charges, the energy vs occurrence rate, the total area of the charge ball, and potentially the dependence of the number of SEUs on the camera elevation. Previously developed noise distribution analysis enables the removal of noise and the detection of low energy SEUs. In addition, it allows estimating the area of the deposited charge. We used two DSLR cameras and measured SEU rates at elevations from sea level to 1088 m, allowing us to explore the dependence of SEU energy and area distributions on elevation. We observed significant increases in SEUs with elevation changes of < 50 meters.
{"title":"Using digital imagers to characterize the dependence of energy and area distributions of SEUs on elevation","authors":"G. Chapman, Rohan Thomas, Klinsmann J. Coelho Silva Meneses, Ruoyi Zhao, I. Koren, Z. Koren","doi":"10.1109/DFT50435.2020.9250888","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250888","url":null,"abstract":"Camera Integrated circuits (ICs) suffer from soft errors known as Single Event Upsets (SEUs). Unlike traditional ICs, camera sensors record the location and energy deposited by each SEU. Camera pixels measure when and where cosmic ray particles hit and store the deposited charge when dark-frame images are taken. Hence, with large datasets of time-lapsed dark-frame images, pixel analysis provides the intensity and energy distribution of deposited SEU charges, the energy vs occurrence rate, the total area of the charge ball, and potentially the dependence of the number of SEUs on the camera elevation. Previously developed noise distribution analysis enables the removal of noise and the detection of low energy SEUs. In addition, it allows estimating the area of the deposited charge. We used two DSLR cameras and measured SEU rates at elevations from sea level to 1088 m, allowing us to explore the dependence of SEU energy and area distributions on elevation. We observed significant increases in SEUs with elevation changes of < 50 meters.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123022009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-19DOI: 10.1109/DFT50435.2020.9250812
Zhen Gao, Xiaohui Wei, Han Zhang, Wenshuo Li, Guangjun Ge, Yu Wang, P. Reviriego
Convolutional Neural Networks (CNNs) are widely used in image classification tasks. To fit the application of CNNs on resource-limited embedded systems, pruning is a popular technique to reduce the complexity of the network. In this paper, the robustness of the pruned network against errors on the network parameters is examined with VGG16 as a case study. The effects of errors on the weights, bias, and batch normalization (BN) parameters are evaluated for the network with different pruning rates based on error injection experiments. The results show that in general networks with more weights pruned are more robust for a given error rate. The effect of multiple errors on bias or BN parameters is almost the same for the networks with different pruning rates that are lower than 90%. Further experiments are performed to explain the bimodal phenomenon of the network performance with errors on the parameters, to find that only errors on 6% of the parameter bits will cause large degradation of the neural network performance.
{"title":"Reliability Evaluation of Pruned Neural Networks against Errors on Parameters","authors":"Zhen Gao, Xiaohui Wei, Han Zhang, Wenshuo Li, Guangjun Ge, Yu Wang, P. Reviriego","doi":"10.1109/DFT50435.2020.9250812","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250812","url":null,"abstract":"Convolutional Neural Networks (CNNs) are widely used in image classification tasks. To fit the application of CNNs on resource-limited embedded systems, pruning is a popular technique to reduce the complexity of the network. In this paper, the robustness of the pruned network against errors on the network parameters is examined with VGG16 as a case study. The effects of errors on the weights, bias, and batch normalization (BN) parameters are evaluated for the network with different pruning rates based on error injection experiments. The results show that in general networks with more weights pruned are more robust for a given error rate. The effect of multiple errors on bias or BN parameters is almost the same for the networks with different pruning rates that are lower than 90%. Further experiments are performed to explain the bimodal phenomenon of the network performance with errors on the parameters, to find that only errors on 6% of the parameter bits will cause large degradation of the neural network performance.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126889243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-19DOI: 10.1109/DFT50435.2020.9250797
Avijit Chakraborty, D. Walker
Delay test is used to verify the timing performance of integrated circuits. The test requires launching rising or falling transitions into the circuit and capturing the results after the specified delay. All the sequential elements in the design are required to be implemented with scan flip-flops such that the captured data can be observed for correct behavior. If the result is captured at a non-scan flip-flop, or a memory, it cannot be read out, resulting in fault coverage loss. This research describes an observability-based algorithm to transfer results captured in non-scan flip-flops to scan flip-flops using low speed functional clock cycles, termed coda cycles, so the results can be read out. We demonstrate the algorithm using path delay test on ISCAS89 benchmark circuits, where a fraction of the scan flip-flops have been made non-scan, and demonstrate the improvement in coverage when adding coda cycles to the clocking method.
{"title":"Observability Driven Path Generation for Delay Test Coverage Improvement in Scan Limited Circuits","authors":"Avijit Chakraborty, D. Walker","doi":"10.1109/DFT50435.2020.9250797","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250797","url":null,"abstract":"Delay test is used to verify the timing performance of integrated circuits. The test requires launching rising or falling transitions into the circuit and capturing the results after the specified delay. All the sequential elements in the design are required to be implemented with scan flip-flops such that the captured data can be observed for correct behavior. If the result is captured at a non-scan flip-flop, or a memory, it cannot be read out, resulting in fault coverage loss. This research describes an observability-based algorithm to transfer results captured in non-scan flip-flops to scan flip-flops using low speed functional clock cycles, termed coda cycles, so the results can be read out. We demonstrate the algorithm using path delay test on ISCAS89 benchmark circuits, where a fraction of the scan flip-flops have been made non-scan, and demonstrate the improvement in coverage when adding coda cycles to the clocking method.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125975818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-19DOI: 10.1109/DFT50435.2020.9250844
C. Bolchini, Luca Cassano, A. Miele, Matteo Biasielli
Image restoration is generally employed to recover an image that has been blurred, for example, for noise suppression purposes. The Richardson-Lucy (RL) algorithm is a widely used iterative approach for image restoration. In this paper we propose a lightweight application-specific fault detection and management scheme for RL that exploits two specific characteristics of such algorithm: i) there is a strong correlation between the input and output images of each iteration, and ii) the algorithm is often able to produce a final output that is very similar to the expected one although the output of an intermediate iteration has been corrupted by a fault. The proposed scheme exploits these characteristics to detect the occurrence of a fault without requiring duplication and to determine whether the error in the output of an intermediate iteration of the algorithm would be absorbed (thus avoiding image dropping and algorithm reexecution) or whether the image has to be discarded and the overall elaboration to be re-executed. An experimental campaign demonstrated that our scheme allows for an execution time reduction of about 54% w.r.t. the classical Duplication with Comparison (DWC), still providing about 99% fault detection.
{"title":"Lightweight Fault Detection and Management for Image Restoration","authors":"C. Bolchini, Luca Cassano, A. Miele, Matteo Biasielli","doi":"10.1109/DFT50435.2020.9250844","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250844","url":null,"abstract":"Image restoration is generally employed to recover an image that has been blurred, for example, for noise suppression purposes. The Richardson-Lucy (RL) algorithm is a widely used iterative approach for image restoration. In this paper we propose a lightweight application-specific fault detection and management scheme for RL that exploits two specific characteristics of such algorithm: i) there is a strong correlation between the input and output images of each iteration, and ii) the algorithm is often able to produce a final output that is very similar to the expected one although the output of an intermediate iteration has been corrupted by a fault. The proposed scheme exploits these characteristics to detect the occurrence of a fault without requiring duplication and to determine whether the error in the output of an intermediate iteration of the algorithm would be absorbed (thus avoiding image dropping and algorithm reexecution) or whether the image has to be discarded and the overall elaboration to be re-executed. An experimental campaign demonstrated that our scheme allows for an execution time reduction of about 54% w.r.t. the classical Duplication with Comparison (DWC), still providing about 99% fault detection.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131213663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-19DOI: 10.1109/DFT50435.2020.9250837
Zhen Gao, Han Zhang, Xiaohui Wei, Tong Yan, Kangkang Guo, Wenshuo Li, Yu Wang, P. Reviriego
Convolutional Neural Networks (CNNs) are widely used in computer vision and natural language processing. Due to large computational requirements, implementation of CNNs on FPGAs becomes an popular option. As CNNs being used in safety critical applications, reliability become a priority. This poses challenges as FPGAs are prone to suffer soft errors. Traditional fault tolerant techniques based on modular redundancy introduce a large overhead, which may not be acceptable for many resources-limited embedded system. This paper explores the use of an ensemble of CNNs to build reliable classifiers. The idea is to combine several “weak” classifiers to obtain a “strong” one, so that the classifier can still work reliably if one of its members fails. Differently from traditional ensemble learning that looks for the classifiers to complement each other, in our case similarity is also important to achieve fault tolerance. To evaluate the potential of using ensembles to implement fault tolerant CNNs, an initial study is done on ResNets. The results show that, relative to a single deep ResNet, an ensemble of shallow ResNets could provide similar classification results while providing an effective protection against errors with limited overhead.
{"title":"Reliable Classification with Ensemble Convolutional Neural Networks","authors":"Zhen Gao, Han Zhang, Xiaohui Wei, Tong Yan, Kangkang Guo, Wenshuo Li, Yu Wang, P. Reviriego","doi":"10.1109/DFT50435.2020.9250837","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250837","url":null,"abstract":"Convolutional Neural Networks (CNNs) are widely used in computer vision and natural language processing. Due to large computational requirements, implementation of CNNs on FPGAs becomes an popular option. As CNNs being used in safety critical applications, reliability become a priority. This poses challenges as FPGAs are prone to suffer soft errors. Traditional fault tolerant techniques based on modular redundancy introduce a large overhead, which may not be acceptable for many resources-limited embedded system. This paper explores the use of an ensemble of CNNs to build reliable classifiers. The idea is to combine several “weak” classifiers to obtain a “strong” one, so that the classifier can still work reliably if one of its members fails. Differently from traditional ensemble learning that looks for the classifiers to complement each other, in our case similarity is also important to achieve fault tolerance. To evaluate the potential of using ensembles to implement fault tolerant CNNs, an initial study is done on ResNets. The results show that, relative to a single deep ResNet, an ensemble of shallow ResNets could provide similar classification results while providing an effective protection against errors with limited overhead.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114808620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-19DOI: 10.1109/dft50435.2020.9250804
{"title":"DFT 2020 Committees","authors":"","doi":"10.1109/dft50435.2020.9250804","DOIUrl":"https://doi.org/10.1109/dft50435.2020.9250804","url":null,"abstract":"","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116864363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-19DOI: 10.1109/DFT50435.2020.9250865
Lucas Matana Luza, D. Söderström, G. Tsiligiannis, H. Puchner, C. Cazzaniga, Ernesto Sánchez, A. Bosio, L. Dilillo
Approximate Computing (AxC) is a well-known paradigm able to reduce the computational and power overheads of a multitude of applications, at the cost of a decreased accuracy. Convolutional Neural Networks (CNNs) have proven to be particularly suited for AxC because of their inherent resilience to errors. However, the implementation of AxC techniques may affect the intrinsic resilience of the application to errors induced by Single Events in a harsh environment. This work introduces an experimental study of the impact of neutron irradiation on approximate computing techniques applied on the data representation of a CNN.
{"title":"Investigating the Impact of Radiation-Induced Soft Errors on the Reliability of Approximate Computing Systems","authors":"Lucas Matana Luza, D. Söderström, G. Tsiligiannis, H. Puchner, C. Cazzaniga, Ernesto Sánchez, A. Bosio, L. Dilillo","doi":"10.1109/DFT50435.2020.9250865","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250865","url":null,"abstract":"Approximate Computing (AxC) is a well-known paradigm able to reduce the computational and power overheads of a multitude of applications, at the cost of a decreased accuracy. Convolutional Neural Networks (CNNs) have proven to be particularly suited for AxC because of their inherent resilience to errors. However, the implementation of AxC techniques may affect the intrinsic resilience of the application to errors induced by Single Events in a harsh environment. This work introduces an experimental study of the impact of neutron irradiation on approximate computing techniques applied on the data representation of a CNN.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130926664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-19DOI: 10.1109/DFT50435.2020.9250843
V. Gupta, D. Pellegrini, S. Khandelwal, A. Jabir, Shahar Kvatinsky, E. Martinelli, C. Natale, M. Ottavi
Sensors give factual and process information about the environment or other physical phenomena. Sensing using memristors has been recently introduced for its potential for high density integration and miniaturization. Complementary Resistive Switch (CRS) based sensor provides an extremely efficient crossbar array that reduces the sneak current. The objective of this paper is to introduce and evaluate a circuit model for sensing using memristive complementary resistive switch. We introduce a reliable SPICE implementation of memristor model that captures the sensing behaviour of memristor. Our simulation results also validate the SPICE model for CRS sensing architecture, whose parameters could be easily adapted to match experimental data. The results also investigate the sensitivity and device behaviour of memristor and CRS sensor device in the presence of oxidizing and reducing gases of different concentration.
{"title":"Sensing with Memristive Complementary Resistive Switch: Modelling and Simulations","authors":"V. Gupta, D. Pellegrini, S. Khandelwal, A. Jabir, Shahar Kvatinsky, E. Martinelli, C. Natale, M. Ottavi","doi":"10.1109/DFT50435.2020.9250843","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250843","url":null,"abstract":"Sensors give factual and process information about the environment or other physical phenomena. Sensing using memristors has been recently introduced for its potential for high density integration and miniaturization. Complementary Resistive Switch (CRS) based sensor provides an extremely efficient crossbar array that reduces the sneak current. The objective of this paper is to introduce and evaluate a circuit model for sensing using memristive complementary resistive switch. We introduce a reliable SPICE implementation of memristor model that captures the sensing behaviour of memristor. Our simulation results also validate the SPICE model for CRS sensing architecture, whose parameters could be easily adapted to match experimental data. The results also investigate the sensitivity and device behaviour of memristor and CRS sensor device in the presence of oxidizing and reducing gases of different concentration.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125574976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-19DOI: 10.1109/DFT50435.2020.9250829
Basma Hajri, Mohammad M. Mansour, A. Chehab, H. Aziza
Recently, the variability of resistive memory devices (RRAM) has become an attractive feature for hardware security in the form of a Physically Unclonable Function (PUF). Although several RRAM-based PUFs have appeared in the literature, they still suffer from some issues related to reliability, reconfigurability, and extensive integration cost. This paper presents a novel lightweight reconfigurable RRAM-based PUF (LRR-PUF) wherein multiple RRAM cells, connected to the same bit line and same transistor (1T4R), are used to generate a single bit response. The pulse programming method used is also innovative and exploits variations in the number of pulses needed to switch the RRAM cell as the primary entropy source of the PUF. The main feature of the proposed PUF is its integration with any RRAM architecture at almost no additional cost. Through extensive simulations, including the impact of temperature and voltage variations along with statistical characterization, we demonstrate that the LRR-PUF exhibits such attractive properties including high reliability (almost 100%), reconfigurability, uniqueness, cost, and efficiency.
{"title":"A Lightweight Reconfigurable RRAM-based PUF for Highly Secure Applications","authors":"Basma Hajri, Mohammad M. Mansour, A. Chehab, H. Aziza","doi":"10.1109/DFT50435.2020.9250829","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250829","url":null,"abstract":"Recently, the variability of resistive memory devices (RRAM) has become an attractive feature for hardware security in the form of a Physically Unclonable Function (PUF). Although several RRAM-based PUFs have appeared in the literature, they still suffer from some issues related to reliability, reconfigurability, and extensive integration cost. This paper presents a novel lightweight reconfigurable RRAM-based PUF (LRR-PUF) wherein multiple RRAM cells, connected to the same bit line and same transistor (1T4R), are used to generate a single bit response. The pulse programming method used is also innovative and exploits variations in the number of pulses needed to switch the RRAM cell as the primary entropy source of the PUF. The main feature of the proposed PUF is its integration with any RRAM architecture at almost no additional cost. Through extensive simulations, including the impact of temperature and voltage variations along with statistical characterization, we demonstrate that the LRR-PUF exhibits such attractive properties including high reliability (almost 100%), reconfigurability, uniqueness, cost, and efficiency.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"273 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121377087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-19DOI: 10.1109/DFT50435.2020.9250906
Soultana Ellinidou, G. Sharma, O. Markowitch, G. Gogniat, J. Dricot
Since the number of processors and cores on a single chip is increasing, the interconnection among them becomes significant. Network-on-Chip (NoC) has direct access to all resources and information within a System-on-Chip (SoC), rendering it appealing to attackers. Malicious attacks targeting NoC are a major cause of performance depletion and they can cause arbitrary behavior of links or routers, that is, Byzantine faults. Byzantine faults have been thoroughly investigated in the context of Distributed systems however not in Very Large Scale Integration (VLSI) systems. Hence, in this paper we propose a novel fault model followed by the design and implementation of lightweight algorithms, based on Software Defined Network-on-Chip (SDNoC) architecture. The proposed algorithms can be used to build highly available NoCs and can tolerate Byzantine faults. Additionally, a set of different scenarios has been simulated and the results demonstrate that by using the proposed algorithms the packet loss decreases between 65% and 76% under Transpose traffic, 67% and 77% under BitReverse and 55% and 66% under Uniform traffic.
{"title":"A novel Network-on-Chip security algorithm for tolerating Byzantine faults","authors":"Soultana Ellinidou, G. Sharma, O. Markowitch, G. Gogniat, J. Dricot","doi":"10.1109/DFT50435.2020.9250906","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250906","url":null,"abstract":"Since the number of processors and cores on a single chip is increasing, the interconnection among them becomes significant. Network-on-Chip (NoC) has direct access to all resources and information within a System-on-Chip (SoC), rendering it appealing to attackers. Malicious attacks targeting NoC are a major cause of performance depletion and they can cause arbitrary behavior of links or routers, that is, Byzantine faults. Byzantine faults have been thoroughly investigated in the context of Distributed systems however not in Very Large Scale Integration (VLSI) systems. Hence, in this paper we propose a novel fault model followed by the design and implementation of lightweight algorithms, based on Software Defined Network-on-Chip (SDNoC) architecture. The proposed algorithms can be used to build highly available NoCs and can tolerate Byzantine faults. Additionally, a set of different scenarios has been simulated and the results demonstrate that by using the proposed algorithms the packet loss decreases between 65% and 76% under Transpose traffic, 67% and 77% under BitReverse and 55% and 66% under Uniform traffic.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127740762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：