Innovative tunnel FET architectures

Abstract

We propose three innovative SOI Tunnel FET architectures. They are evaluated and compared with a standard TFET structure using Sentaurus TCAD. The extension of the source (anode) at the bottom of the body generates vertical band-to-band tunneling with a very steep slope and higher ION than lateral tunneling, but only for gate lengths longer than 100 nm. Using a heavily doped boron thin layer at the bottom increases ION even for aggressive gate lengths. Implementation of a tip in the source provides performance similar to the reference TFET. TCAD simulation using SiGe instead of Si shows current drive increase when using the thin boron layer for very thin channels, even for shorter gate lengths.