Design optimization of gate-all-around vertical nanowire transistors for future memory applications

Abstract

This paper investigates the application of gate-all-around (GAA) vertical nanowire transistors (VNWFET) as an access element in future non-volatile memories (NVM) such as resistive random-access memory (RRAM), phase-change random access memory (PCRAM) and spin-torque-transfer memory (STT-RAM or MRAM). We primarily choose direct-current (DC) parameters ION and ION/IOFF as our figure of merit (FOM) and optimize the vertical nanowire FET by taking various critical process parameters into account such as channel length, fin doping, gate overlap, and cross-sectional shape of the nanowire transistor. Further, using the optimized device in a 3×3 cross-bar array arrangement, we evaluate the read/write disturb due to the active device on it's neighboring inactive devices. We show that the optimized access device can be used for a range of currents ratings required by different memory devices, ION being as high as 0.19 A/μm2 and IOFF being as low as 2 nA/μm2.