Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628158
Sheng Sun, Lijun Jiang, W. Chew
This paper presents a brief review and recent development of surface integral equation solvers for multiscale interconnects and circuits modeling. As the future production processes down to 5 nm and the operating frequency increases, both multi-scale and large-scale natures should be taken into account in the electromagnetic simulations. Fast, efficient, stable, and broadband integral equation based solvers become indispensable when millions or ten s of millions of unknowns might be involved in the simulation of the integrated circuit. Recent progress and our latest researches in the development of broadband fast electromagnetic solvers will be demonstrated.
{"title":"Recent development of surface integral equation solvers for multiscale interconnects and circuits","authors":"Sheng Sun, Lijun Jiang, W. Chew","doi":"10.1109/EDSSC.2013.6628158","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628158","url":null,"abstract":"This paper presents a brief review and recent development of surface integral equation solvers for multiscale interconnects and circuits modeling. As the future production processes down to 5 nm and the operating frequency increases, both multi-scale and large-scale natures should be taken into account in the electromagnetic simulations. Fast, efficient, stable, and broadband integral equation based solvers become indispensable when millions or ten s of millions of unknowns might be involved in the simulation of the integrated circuit. Recent progress and our latest researches in the development of broadband fast electromagnetic solvers will be demonstrated.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121029005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628171
M. Cao, Xuezhen Cheng, Yu Hong
In this paper, a detection sensor is designed. The mathematics and simulation models based on the charge induction mechanism are built. The characteristics of the sensor are developed by using the finite-element method. A method combined by GA (genetic algorithm) and ANSYS is introduced to analyses the optimal sensitive response. The performance has been evaluated. And the device with three probe scales in series illustrates that the dimension of the device is the most sensitivity issue. At same time, a new measurement system based on the differential principles with three probe device is proposed.
{"title":"The advanced sensor applied to the dust-charged detection","authors":"M. Cao, Xuezhen Cheng, Yu Hong","doi":"10.1109/EDSSC.2013.6628171","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628171","url":null,"abstract":"In this paper, a detection sensor is designed. The mathematics and simulation models based on the charge induction mechanism are built. The characteristics of the sensor are developed by using the finite-element method. A method combined by GA (genetic algorithm) and ANSYS is introduced to analyses the optimal sensitive response. The performance has been evaluated. And the device with three probe scales in series illustrates that the dimension of the device is the most sensitivity issue. At same time, a new measurement system based on the differential principles with three probe device is proposed.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121063051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628081
W. Yeh, C. Lai, L. Chin, Po-Ying Chen
In this work, we investigate the impact of substrate doping concentration on device characteristic variation and sensitivity to substrate bias for ultra-thin body and bulk oxide SOI MOSFET. We found that high substrate dose device suffer from unsymmetrical and variance in device's characteristics. Compared to high dose substrate UTBB-SOI device, low dose substrate device characteristic is less sensitive to substrate back bias. And we found that low substrate dose SOI device which with lower impact ionization shows better device's reliability than the high substrate dose one does.
{"title":"Device variability and reliability check for ultra-thin-body and bulk oxide CMOSFETs","authors":"W. Yeh, C. Lai, L. Chin, Po-Ying Chen","doi":"10.1109/EDSSC.2013.6628081","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628081","url":null,"abstract":"In this work, we investigate the impact of substrate doping concentration on device characteristic variation and sensitivity to substrate bias for ultra-thin body and bulk oxide SOI MOSFET. We found that high substrate dose device suffer from unsymmetrical and variance in device's characteristics. Compared to high dose substrate UTBB-SOI device, low dose substrate device characteristic is less sensitive to substrate back bias. And we found that low substrate dose SOI device which with lower impact ionization shows better device's reliability than the high substrate dose one does.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127516116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628044
A. Rasmi, I. M. Azmi, A. Rahim, H. Hsu, E. Chang
Summary form only given. This paper presents the design and simulated performance of millimeter-wave monolithic microwave integrated circuit (MMIC) low noise amplifier (LNA). A two stage LNA has been designed and developed using a 0.15um commercial GaAs pseudomorphic HEMT technology. The simulated data shows 2.21dB of noise figure with an associated gain of 13.14dB at the frequency operation of 30 GHz. At 3.0V of drain voltage, VDS and -0.20V of gate voltage, VGS; this LNA consume 56mA of total current and achieves 16.10dBm of output P1dB. The layout size is 4.1 × 1.3 mm2.
{"title":"30 GHz 2-stage MMIC low noise amplifier using GaAs pseudomorphic HEMT","authors":"A. Rasmi, I. M. Azmi, A. Rahim, H. Hsu, E. Chang","doi":"10.1109/EDSSC.2013.6628044","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628044","url":null,"abstract":"Summary form only given. This paper presents the design and simulated performance of millimeter-wave monolithic microwave integrated circuit (MMIC) low noise amplifier (LNA). A two stage LNA has been designed and developed using a 0.15um commercial GaAs pseudomorphic HEMT technology. The simulated data shows 2.21dB of noise figure with an associated gain of 13.14dB at the frequency operation of 30 GHz. At 3.0V of drain voltage, VDS and -0.20V of gate voltage, VGS; this LNA consume 56mA of total current and achieves 16.10dBm of output P1dB. The layout size is 4.1 × 1.3 mm2.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124996708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628235
Z. Ahmed, M. Chan
Strain incorporated surface potential based compact model for Carbon Nanotube field effect transistor (CNTFET) is presented in this paper. The model is first of its kind and confers strain phenomena by accounting for the induced change in band-gap and corresponding energy band opening near the Fermi-level of the CNTFET in source exhaustion regime.
{"title":"Strain modeling in source exhaustion regime of Carbon nanotube field effect transistor","authors":"Z. Ahmed, M. Chan","doi":"10.1109/EDSSC.2013.6628235","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628235","url":null,"abstract":"Strain incorporated surface potential based compact model for Carbon Nanotube field effect transistor (CNTFET) is presented in this paper. The model is first of its kind and confers strain phenomena by accounting for the induced change in band-gap and corresponding energy band opening near the Fermi-level of the CNTFET in source exhaustion regime.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125501275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628090
Hongyu He, Jin He, W. Deng, Hao Wang, Yue Hu, Xiaoan Zhu, Xueren Zheng
A simple leakage current expression is presented for the polycrystalline silicon nanowire thin-film transistors. The thermal field emission mechanism is utilized to derive the expression. The model results are compared with the experimental data at different temperatures and voltages, and good agreements are obtained.
{"title":"A simple leakage current model for polycrystalline silicon nanowire thin-film transistors","authors":"Hongyu He, Jin He, W. Deng, Hao Wang, Yue Hu, Xiaoan Zhu, Xueren Zheng","doi":"10.1109/EDSSC.2013.6628090","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628090","url":null,"abstract":"A simple leakage current expression is presented for the polycrystalline silicon nanowire thin-film transistors. The thermal field emission mechanism is utilized to derive the expression. The model results are compared with the experimental data at different temperatures and voltages, and good agreements are obtained.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116392375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628237
X. Huang, P. Lai
BaTiO3 with and without Hf incorporation was studied as charge-trapping layer (CTL) for flash memory applications. Comparing with the device with BaTiO3 CTL, the one with Hf-doped BaTiO3 shows better performance in terms of higher program speed and better data retention due to suppressed leakage by Hf incorporated in BaTiO3. Therefore, the Hf-doped BaTiO3 is a promising candidate as CTL for flash memory application.
{"title":"Improved performance of Hf-doped BaTiO3 as charge-traping layer for flash memory applications","authors":"X. Huang, P. Lai","doi":"10.1109/EDSSC.2013.6628237","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628237","url":null,"abstract":"BaTiO<sub>3</sub> with and without Hf incorporation was studied as charge-trapping layer (CTL) for flash memory applications. Comparing with the device with BaTiO<sub>3</sub> CTL, the one with Hf-doped BaTiO<sub>3</sub> shows better performance in terms of higher program speed and better data retention due to suppressed leakage by Hf incorporated in BaTiO<sub>3</sub>. Therefore, the Hf-doped BaTiO<sub>3</sub> is a promising candidate as CTL for flash memory application.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116448743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628095
Chun Yang, Xiaole Cui, Bo Wang, Chung-Len Lee
A new CMOS curvature compensated bandgap reference circuit which uses two different types of material to realize its resistors in an improved structure is presented. Implemented in a 0.18 μm technology, it achieves performance of a temperature coefficient of 1.8 ppm/°C over 0 ~ 100°C, a line regulation of 0.017%/V over the range 1.2 ~3 V and a power supply rejection ratio of 82 dB@1 Hz. It can offer a reference voltage of 1.1 V but occupy an area of only 0.049 mm2.
{"title":"A 1.8ppm/°C Low Temperature Coefficient Curvature Compensated Bandgap for the Low Voltage Application","authors":"Chun Yang, Xiaole Cui, Bo Wang, Chung-Len Lee","doi":"10.1109/EDSSC.2013.6628095","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628095","url":null,"abstract":"A new CMOS curvature compensated bandgap reference circuit which uses two different types of material to realize its resistors in an improved structure is presented. Implemented in a 0.18 μm technology, it achieves performance of a temperature coefficient of 1.8 ppm/°C over 0 ~ 100°C, a line regulation of 0.017%/V over the range 1.2 ~3 V and a power supply rejection ratio of 82 dB@1 Hz. It can offer a reference voltage of 1.1 V but occupy an area of only 0.049 mm2.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128416322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel symmetric n-type lateral diffusion MOS (sym-nLDMOS) is presented. Fabricated without any extra mask in a standard 0.18 μm 60 V SOI BCD process, the new sym-nLDMOS has an ability of electrostatic discharge (ESD) self-protection. The TLP measured results show about 1X improvement of It2 in the novel sym-nLDMOS. The output characteristics of the novel device are also be measured.
本文介绍了一种新型对称 n 型横向扩散 MOS（sym-nLDMOS）。新型 sym-nLDMOS 采用标准 0.18 μm 60 V SOI BCD 工艺制造，无需任何额外掩模，具有静电放电（ESD）自我保护能力。TLP 测量结果显示，新型 sym-nLDMOS 的 It2 提高了约 1 倍。此外，还测量了新型器件的输出特性。
{"title":"A novel ESD self-protecting symmetric nLDMOS for 60V SOI BCD process","authors":"Y. Wang, Guangyi Lu, Jian Cao, Qi Liu, Ganggang Zhang, Xing Zhang","doi":"10.1109/EDSSC.2013.6628102","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628102","url":null,"abstract":"A novel symmetric n-type lateral diffusion MOS (sym-nLDMOS) is presented. Fabricated without any extra mask in a standard 0.18 μm 60 V SOI BCD process, the new sym-nLDMOS has an ability of electrostatic discharge (ESD) self-protection. The TLP measured results show about 1X improvement of It2 in the novel sym-nLDMOS. The output characteristics of the novel device are also be measured.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128544991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628182
Ru Huang, Qianqian Huang, Zhan Zhan, Chunlei Wu, Y. Qiu, Yangyuan Wang
In this paper, two novel silicon-based TFETs are discussed, including Si junction-modulated TFET (JTFET) with the equivalent function to achieve ideally abrupt doping profile and multi-finger-gate TFET of dopant-segregated Schottky Barrier source (mFSB-TFET) with adaptive operation mechanism for better performance tradeoff.
{"title":"Novel silicon-based tunneling FET with junction engineering and gate configuration for low power applications (invited)","authors":"Ru Huang, Qianqian Huang, Zhan Zhan, Chunlei Wu, Y. Qiu, Yangyuan Wang","doi":"10.1109/EDSSC.2013.6628182","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628182","url":null,"abstract":"In this paper, two novel silicon-based TFETs are discussed, including Si junction-modulated TFET (JTFET) with the equivalent function to achieve ideally abrupt doping profile and multi-finger-gate TFET of dopant-segregated Schottky Barrier source (mFSB-TFET) with adaptive operation mechanism for better performance tradeoff.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128586013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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