Incorporating process induced effects into RC extraction

Abstract

With the advent of deep-submicron technologies, more and more process-induced effects become first-order influences to the performance of VLSI chips. In this paper we will describe a set of wafer-level electrical measurement methods which we have used to measure process-induced effects for several deep-submicron technologies. Seven important interconnect performance parameters have been identified as a minimum set of parameters needed to accurately accommodate the effects and predict the resistance and capacitance of the state-of-the-art interconnect systems. Therefore, interconnect parasitic estimation, or interchangeably in this paper, RC extraction, has to be improved to incorporate those parameters. It is also essential that process/TCAD describes those parameters in a format that allows more accurate parasitic estimation.