A 4 Mb 5 V-only flash EEPROM with sector erase

H. Stiegler, B. Ashmore, R. Bussey, M. Gill, S. Lin, M. McConnell, D. McElroy, J. Schreck, P. Shah, P. Truong, A. Esquivel, J. Paterson, B. Riemenschneider
{"title":"A 4 Mb 5 V-only flash EEPROM with sector erase","authors":"H. Stiegler, B. Ashmore, R. Bussey, M. Gill, S. Lin, M. McConnell, D. McElroy, J. Schreck, P. Shah, P. Truong, A. Esquivel, J. Paterson, B. Riemenschneider","doi":"10.1109/VLSIC.1990.111116","DOIUrl":null,"url":null,"abstract":"A full 4-Mb flash EEPROM was fabricated in 0.8-μm CMOS and its functionality was verified. Conservative 1.0-μm features were used in the periphery, resulting in a die area of 95 mm2. The device features 5-V-only operation and either full-chip or sector erase. A segmented architecture, remote row decode, and innovative design techniques provide the sector erase feature and high-voltage handling with improved breakdown protection and isolation","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1990.111116","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5

Abstract

A full 4-Mb flash EEPROM was fabricated in 0.8-μm CMOS and its functionality was verified. Conservative 1.0-μm features were used in the periphery, resulting in a die area of 95 mm2. The device features 5-V-only operation and either full-chip or sector erase. A segmented architecture, remote row decode, and innovative design techniques provide the sector erase feature and high-voltage handling with improved breakdown protection and isolation
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具有扇区擦除功能的4mb 5v -only闪存EEPROM
在0.8 μ m CMOS上制作了一个完整的4mb闪存EEPROM,并对其功能进行了验证。外围采用保守的1.0-μm特征,导致模具面积为95 mm2。该器件具有仅5v操作和全芯片或扇区擦除功能。分段架构、远程行解码和创新的设计技术提供了扇区擦除功能和高压处理,并改进了击穿保护和隔离
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