A 3.3 V/1 W class D audio power amplifier with 103 dB DR and 90% efficiency

2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595) Pub Date : 2002-08-07 DOI:10.1109/MIEL.2002.1003324

V.M. Tousi, F. Sahandi, M. Atarodi, M. Shojaei

引用次数: 12

Abstract

A single-chip Integrated circuit of 3.3 V/1 W class-D high fidelity and high efficiency audio power amplifier is presented in this paper. The design has been done using a 3.3 V/0.25 /spl mu/m CMOS process. The maximum output power is 1 W before the amplifier saturates. The THD+N at 0.5 W output power is below 0.03% and efficiency is better than 90% thanks to the careful design of the output stage. The dynamic range is more than 100 dB suitable for high fidelity audio applications. A single-loop single-bit third order sigma-delta modulator is used to generate the PWM signal from input audio signal. The PWM signal is then filtered at the output with a second order low pass filter external to the chip to regenerate the input signal.

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3.3 V/ 1w D类音频功率放大器，DR为103 dB，效率为90%

介绍了一种3.3 V/ 1w的d类高保真高效音频功率放大器的单片机集成电路。设计采用3.3 V/0.25 /spl μ m CMOS工艺。放大器饱和前的最大输出功率为1w。由于输出级的精心设计，0.5 W输出功率下的THD+N低于0.03%，效率优于90%。动态范围超过100 dB，适合高保真音频应用。采用单回路单比特三阶σ - δ调制器从输入音频信号中产生PWM信号。然后用芯片外部的二阶低通滤波器在输出端对PWM信号进行滤波，以重新生成输入信号。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)

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