{"title":"Q20D080 analog RAM logic array","authors":"C. Blake, M. Hollabaugh","doi":"10.1109/CICC.1989.56762","DOIUrl":null,"url":null,"abstract":"An ECL (emitter-coupled logic)-structured array containing 1520 logic cells, 2560 bits of RAM, and a customizable analog section is described. The special needs of high performance VLSI testers was the driving force behind its organization and architecture. The chip is fabricated with a trench isolation bipolar process with 1-μm features, double layers of polysilicon, and triple layers of metallization","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1989.56762","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
An ECL (emitter-coupled logic)-structured array containing 1520 logic cells, 2560 bits of RAM, and a customizable analog section is described. The special needs of high performance VLSI testers was the driving force behind its organization and architecture. The chip is fabricated with a trench isolation bipolar process with 1-μm features, double layers of polysilicon, and triple layers of metallization
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