Ultra-low-voltage current-sense read circuits for CMOS SOI SRAMs

Abstract

For SRAM circuits operated at 0.5V reliable readout of the stored information is challenging due to a voltage swing of tens of mV. Two readout topologies described in this paper for ultra-low-voltage (ULV) SOI-CMOS SRAMs exploit unique features of partially-depleted (PD)-SOI transistors to perform current rather than voltage sensing. The analysis presented leads to the dimensioning of the sense amplifier transistors for robust operation with a maximum number of cells per column of the SRAM. Simulations of the presented circuits demonstrate that the information stored in an SRAM with a four-transistor CMOS-SOI cell can be reliably accessed in 3ns with 180nW power consumption.