Hiroshi Yamamoto, K. Kikuchi, N. Ui, Kazutaka Inoue, V. Vadalà, G. Bosi, A. Raffo, G. Vannini
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引用次数: 1
Abstract
This paper describes the influence of gate-voltage clipping behavior on drain efficiency in case of class-F and inverse class-F $(\mathbf{F}^{-1})$ operations under saturated regime. Numerical analysis using a simplified transistor model was carried out. As a result, we have demonstrated that the limiting factor for $\mathbf{class}-\mathbf{F}^{-1}$ operation is the gate-diode conduction rather than knee voltage. On the other hand, class-F PA is restricted by the knee voltage effects. Furthermore, nonlinear measurements carried out on a GaN HEMT support our analytical results.