Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8550914
V. Issakov, Sebastian Kehl-Waas, R. Ciocoveanu, W. Simbürger, A. Geiselbrechtinger
This paper presents a low-power, ESD-protected 24 GHz single-ended input to differential output single-stage cascode LNA in Infineon's SiGe BiCMOS technology. The proposed circuit uses bridged T-coils as loads to provide an inductive voltage divider for impedance transformation and extend the bandwidth. To reduce power consumption, the circuit operates from a low supply voltage of 1.5 V. Therefore, to compensate for reduced linearity the circuit uses a multi-tanh doublet. At the center frequency of 24 GHz the amplifier offers a gain of 12 dB and a noise figure of 2.6 dB including the on-chip input balun. The circuit exhibits a competitive linearity of −10 dBm input-referred 1dB compression point at 24 GHz. The LNA consumes 18 mA from a single 1.5 V supply. The ESD hardness has been investigated using an HBM pulse generator. The circuit exhibits a 6 kV HBM hardness at the input RF pin. The chip size including the pads is 0.49 mm2.
{"title":"A 6 kV ESD-Protected Low-Power 24 GHz LNA for Radar Applications in SiGe BiCMOS","authors":"V. Issakov, Sebastian Kehl-Waas, R. Ciocoveanu, W. Simbürger, A. Geiselbrechtinger","doi":"10.1109/BCICTS.2018.8550914","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8550914","url":null,"abstract":"This paper presents a low-power, ESD-protected 24 GHz single-ended input to differential output single-stage cascode LNA in Infineon's SiGe BiCMOS technology. The proposed circuit uses bridged T-coils as loads to provide an inductive voltage divider for impedance transformation and extend the bandwidth. To reduce power consumption, the circuit operates from a low supply voltage of 1.5 V. Therefore, to compensate for reduced linearity the circuit uses a multi-tanh doublet. At the center frequency of 24 GHz the amplifier offers a gain of 12 dB and a noise figure of 2.6 dB including the on-chip input balun. The circuit exhibits a competitive linearity of −10 dBm input-referred 1dB compression point at 24 GHz. The LNA consumes 18 mA from a single 1.5 V supply. The ESD hardness has been investigated using an HBM pulse generator. The circuit exhibits a 6 kV HBM hardness at the input RF pin. The chip size including the pads is 0.49 mm2.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115683759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8551100
Anup P. Omprakash, Adrian Ildefonso, George N. Tzintzarov, J. Babcock, R. Mukhopadhyay, J. Cressler
The present work demonstrates the use of SiGe-on-SOI heterojunction bipolar transistors (HBTs) to implement analog building blocks that can operate from 24°Cto 300°C. A method to calibrate a Mextram compact model over this wide-temperature range is highlighted. Using a calibrated compact model, three different analog building blocks, a current mirror, a bandgap reference (BGR) circuit, and a Class-AB push-pull output stage, were designed, fabricated, and measured from 24°Cto 300°C. The cascode current mirror shows excellent output resistance $(>mathbf{60 M}Omega)$ and low mismatch ratio $(< mathbf{3}%)$ up to 300°C. A modular design approach for building a wide-temperature BGR is proposed. The designed BGR is shown to have a temperature coefficient (TC) of 88.28 ppm/°Cfrom 24°Cto 300°C, which, to the best of the authors' knowledge, is the lowest measured TC of any silicon-based BGR over this temperature range. Long-term operation of the BGR at 300°Cwas verified, and the output voltage was found to vary by less than 0.1%, which makes it robust for high-temperature operation. A Class-AB push-pull output stage is shown operational up to 300°C, and a current drive up to 1 mA and a quiescent current of $mathbf{21} mumathbf{A}$ is measured at 300°C.
目前的工作展示了使用SiGe-on-SOI异质结双极晶体管(hbt)来实现可以在24°C至300°C范围内工作的模拟构建模块。在这个宽温度范围内校准Mextram紧凑型模型的方法被强调。使用校准过的紧凑型模型，设计、制造了三种不同的模拟模块，一个电流反射镜，一个带隙参考(BGR)电路和一个ab级推挽输出级，并在24°C至300°C范围内进行了测量。级联码电流反射镜具有优异的输出电阻$(>mathbf{60 M}Omega)$和低失配比$(< mathbf{3}%)$，最高可达300°C。提出了一种构建宽温BGR的模块化设计方法。设计的BGR在24°C至300°C范围内的温度系数(TC)为88.28 ppm/°C，据作者所知，这是在该温度范围内任何硅基BGR中测量到的最低TC。验证了BGR在300°c下的长期运行，发现输出电压的变化小于0.1%, which makes it robust for high-temperature operation. A Class-AB push-pull output stage is shown operational up to 300°C, and a current drive up to 1 mA and a quiescent current of $mathbf{21} mumathbf{A}$ is measured at 300°C.
{"title":"Using SiGe-on-SOI HBTs to Build 300°C Capable Analog Circuits","authors":"Anup P. Omprakash, Adrian Ildefonso, George N. Tzintzarov, J. Babcock, R. Mukhopadhyay, J. Cressler","doi":"10.1109/BCICTS.2018.8551100","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8551100","url":null,"abstract":"The present work demonstrates the use of SiGe-on-SOI heterojunction bipolar transistors (HBTs) to implement analog building blocks that can operate from 24°Cto 300°C. A method to calibrate a Mextram compact model over this wide-temperature range is highlighted. Using a calibrated compact model, three different analog building blocks, a current mirror, a bandgap reference (BGR) circuit, and a Class-AB push-pull output stage, were designed, fabricated, and measured from 24°Cto 300°C. The cascode current mirror shows excellent output resistance $(>mathbf{60 M}Omega)$ and low mismatch ratio $(< mathbf{3}%)$ up to 300°C. A modular design approach for building a wide-temperature BGR is proposed. The designed BGR is shown to have a temperature coefficient (TC) of 88.28 ppm/°Cfrom 24°Cto 300°C, which, to the best of the authors' knowledge, is the lowest measured TC of any silicon-based BGR over this temperature range. Long-term operation of the BGR at 300°Cwas verified, and the output voltage was found to vary by less than 0.1%, which makes it robust for high-temperature operation. A Class-AB push-pull output stage is shown operational up to 300°C, and a current drive up to 1 mA and a quiescent current of $mathbf{21} mumathbf{A}$ is measured at 300°C.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"4 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114667496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8551078
M. Schröter, Sophia Falk
The theory of high-current effects in bipolar transistors is reviewed. Widely used concepts such as Kirk-effect, base widening, high current density limit, and the calculation of the small-signal storage time are discussed. Misconceptions resulting from incorrect interpretations of the device physics are pointed out and their impact on compact modeling is quantitatively demonstrated based on device simulation.
{"title":"Modeling High-Current Effects in Bipolar Transistors: A Theory Review","authors":"M. Schröter, Sophia Falk","doi":"10.1109/BCICTS.2018.8551078","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8551078","url":null,"abstract":"The theory of high-current effects in bipolar transistors is reviewed. Widely used concepts such as Kirk-effect, base widening, high current density limit, and the calculation of the small-signal storage time are discussed. Misconceptions resulting from incorrect interpretations of the device physics are pointed out and their impact on compact modeling is quantitatively demonstrated based on device simulation.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114943731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8551002
A. Joseph, V. Jain, S. N. Ong, R. Wolf, S. Lim, Jagar Singh
Over the last few decades, SiGe BiCMOS has survived the continued onslaught of RF-CMOS technologies. SiGe HBT invented in late 1980's and later introduced as a BiCMOS technology served as a sweet spot in the emerging RF market, thanks to the SiGe HBT's higher power and better noise characteristics. It did not take very long for RFCMOS scaling roadmap to catch up to SiGe HBT performance levels and displace it from high-volume market segment like RF cellular transceivers. Now with the advent of 5G millimeter-wave (mmWave) applications demanding higher power and lower noise for the front-end, will SiGe BiCMOS once again come back to the forefront to address this market? In this paper we will take a closer look at some of the key aspects of a 130 / 90nm SiGe BiCMOS relative to a 28nm bulk RFCMOS technology for addressing mmWave front-end as well as potential opportunities that lie ahead with scaling.
{"title":"Technology Positioning for mm Wave Applications: 130/90nm SiGe BiCMOS vs. 28nm RFCMOS","authors":"A. Joseph, V. Jain, S. N. Ong, R. Wolf, S. Lim, Jagar Singh","doi":"10.1109/BCICTS.2018.8551002","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8551002","url":null,"abstract":"Over the last few decades, SiGe BiCMOS has survived the continued onslaught of RF-CMOS technologies. SiGe HBT invented in late 1980's and later introduced as a BiCMOS technology served as a sweet spot in the emerging RF market, thanks to the SiGe HBT's higher power and better noise characteristics. It did not take very long for RFCMOS scaling roadmap to catch up to SiGe HBT performance levels and displace it from high-volume market segment like RF cellular transceivers. Now with the advent of 5G millimeter-wave (mmWave) applications demanding higher power and lower noise for the front-end, will SiGe BiCMOS once again come back to the forefront to address this market? In this paper we will take a closer look at some of the key aspects of a 130 / 90nm SiGe BiCMOS relative to a 28nm bulk RFCMOS technology for addressing mmWave front-end as well as potential opportunities that lie ahead with scaling.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114137974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8550951
K. Kellogg, S. Khandelwal, N. Craig, L. Dunleavy
In this paper, we present a detailed analysis on the impact of the presence of gate connected field-plate towards the source contact (GFP-S) on the high-frequency performance of GaN based high-electron mobility transistors (GaN HEMTs). We have developed an accurate physics-based model for GFP-S by enhancing the recent industry standard Advance SPICE Model for GaN HEMTs. It is found that GFP-S affects the non-linear capacitance of GaN HEMTs, thereby impacting small-and large-signal RF performance of these devices. A modification of the ASM model is described that captures these effects. The modified model is validated with measured data on a GFP-S GaN HEMT device.
在本文中，我们详细分析了栅极连接的场极板对GaN基高电子迁移率晶体管(GaN HEMTs)高频性能的影响。我们通过增强GaN hemt的最新行业标准Advance SPICE模型，为GFP-S开发了精确的基于物理的模型。研究发现GFP-S会影响GaN hemt的非线性电容，从而影响这些器件的小信号和大信号射频性能。本文描述了对ASM模型的修改，以捕捉这些效果。用GFP-S GaN HEMT器件上的测量数据验证了改进的模型。
{"title":"Improved Charge Modeling of Field-Plate Enhanced AlGaN/GaN HEMT Devices Using a Physics Based Compact Model","authors":"K. Kellogg, S. Khandelwal, N. Craig, L. Dunleavy","doi":"10.1109/BCICTS.2018.8550951","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8550951","url":null,"abstract":"In this paper, we present a detailed analysis on the impact of the presence of gate connected field-plate towards the source contact (GFP-S) on the high-frequency performance of GaN based high-electron mobility transistors (GaN HEMTs). We have developed an accurate physics-based model for GFP-S by enhancing the recent industry standard Advance SPICE Model for GaN HEMTs. It is found that GFP-S affects the non-linear capacitance of GaN HEMTs, thereby impacting small-and large-signal RF performance of these devices. A modification of the ASM model is described that captures these effects. The modified model is validated with measured data on a GFP-S GaN HEMT device.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"18 782 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128705680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8550855
Xuan-Quang Du, M. Grozing, M. Berroth
A majority of HBT-based track and hold circuits (T/H) with more than 10 GS/s use switched emitter followers (SEFs) as their primary sampling element. The SEFs enable high sampling rates and high analog tracking bandwidths. At high input frequencies, however, they suffer from strong linearity degradations due to base-emitter modulation, signal feedthrough and clock jitter. To address these issues, this work presents a current-mode T/H based on charge sampling. The T/H is implemented in a 130 nm SiGe BiCMOS technology and achieves more than 5 ENOB and more than 33 dBc SFDR up to the 2nd Nyquist frequency at 25.6 GS/s. Time-domain measurements for a 40 GHz input signal are also presented, in which an ENOB of 5.8 and SFDR of 44.6 dBc are achieved.
{"title":"A 25.6-GS/s 40-GHz 1-dB BW Current-Mode Track and Hold Circuit with more than 5-ENOB","authors":"Xuan-Quang Du, M. Grozing, M. Berroth","doi":"10.1109/BCICTS.2018.8550855","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8550855","url":null,"abstract":"A majority of HBT-based track and hold circuits (T/H) with more than 10 GS/s use switched emitter followers (SEFs) as their primary sampling element. The SEFs enable high sampling rates and high analog tracking bandwidths. At high input frequencies, however, they suffer from strong linearity degradations due to base-emitter modulation, signal feedthrough and clock jitter. To address these issues, this work presents a current-mode T/H based on charge sampling. The T/H is implemented in a 130 nm SiGe BiCMOS technology and achieves more than 5 ENOB and more than 33 dBc SFDR up to the 2nd Nyquist frequency at 25.6 GS/s. Time-domain measurements for a 40 GHz input signal are also presented, in which an ENOB of 5.8 and SFDR of 44.6 dBc are achieved.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124781635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8551144
H. Al-Rubaye, Gabriel M. Rebeiz
This paper presents a DC-60 GHz I/Q modulator/transmitter chip in 45 nm SOI CMOS, that can serve as a critical building block for next generation multi-standard and high-capacity wireless backhaul links. The modulator consists of a wideband quadrature signal generator, wideband buffers and two current-combined DC-100 GHz low-noise double-balanced mixers driven in quadrature. The 1.4mm2modulator chip achieves 60 dB of dynamic range in a 1 GHz bandwidth, with an OP1dB of −10 to −12 dBm, thus enabling spectrally-efficient high-order modulation schemes such as 256-QAM. The I/Q modulator achieves 200 Gbps in 16-QAM (50 Gbaud/s), while consuming 200 mW, resulting in record 1 pJ/bit modulation efficiency. In addition to backhaul links, the modulator is an attractive and cost-effective alternative to short-range optical links for data center interconnects (DCI) applications.
{"title":"A DC-60 GHz I/Q Modulator in 45 nm SOI CMOS for Ultra-Wideband 5G Radios","authors":"H. Al-Rubaye, Gabriel M. Rebeiz","doi":"10.1109/BCICTS.2018.8551144","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8551144","url":null,"abstract":"This paper presents a DC-60 GHz I/Q modulator/transmitter chip in 45 nm SOI CMOS, that can serve as a critical building block for next generation multi-standard and high-capacity wireless backhaul links. The modulator consists of a wideband quadrature signal generator, wideband buffers and two current-combined DC-100 GHz low-noise double-balanced mixers driven in quadrature. The 1.4mm2modulator chip achieves 60 dB of dynamic range in a 1 GHz bandwidth, with an OP1dB of −10 to −12 dBm, thus enabling spectrally-efficient high-order modulation schemes such as 256-QAM. The I/Q modulator achieves 200 Gbps in 16-QAM (50 Gbaud/s), while consuming 200 mW, resulting in record 1 pJ/bit modulation efficiency. In addition to backhaul links, the modulator is an attractive and cost-effective alternative to short-range optical links for data center interconnects (DCI) applications.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127041823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8550932
M. Sadeah Dadash, D. Harame, Sorin P. Voiniaescu
High bandwidth and high datarate large-swing optical-modulator-driver and 5G-PA output stages are reported. These series-stacked n-MOS and CMOS cascodes employ a new varactor-based scheme for output resistance and output swing tuning, without affecting the imaginary part of the output impedance and without placing matching networks on the signal path. Record 18Gb/s 64-QAM constellations with EVM lower than −30 dB at 10 dBm output power were measured at 5.5 GHz and 28 GHz, as well as 112 Gb/s (4-PAM) operation with $2.4mathbf{V}_{mathbf{pp}}$ output swing when the cascodes are used as linear broadband optical modulator drivers. The saturated output power, $pmb{P}_{mathbf{SAT}}$, of a single-ended stacked CMOS stage remains larger than 17 dBm from 1 to 45 GHz, with a peak of 19 dBm and PAE of 53.8% at 5.5 GHz, without any input and output matching network. A 4x MIMO transmitter with a differential version of the stacked CMOS output stage would meet the targeted 5G $pmb{P}_{mathbf{SAT}}$ of 28 dBm from 0.5 to 28 GHz. These results suggest that a single CMOS transceiver and PA could cover all the 5G bands from 0.5 GHz to 45 GHz. The n-MOSFET cascodes show better PAE above 10 GHz (33.4% at 28 GHz) than the CMOS version but with 1–2 dB lower $pmb{P}_{text{SAT}}$ and linearity.
{"title":"Large-Swing 22nm Si/SiGe FDSOI Stacked Cascodes for 56GBaud Drivers and 5G PAs","authors":"M. Sadeah Dadash, D. Harame, Sorin P. Voiniaescu","doi":"10.1109/BCICTS.2018.8550932","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8550932","url":null,"abstract":"High bandwidth and high datarate large-swing optical-modulator-driver and 5G-PA output stages are reported. These series-stacked n-MOS and CMOS cascodes employ a new varactor-based scheme for output resistance and output swing tuning, without affecting the imaginary part of the output impedance and without placing matching networks on the signal path. Record 18Gb/s 64-QAM constellations with EVM lower than −30 dB at 10 dBm output power were measured at 5.5 GHz and 28 GHz, as well as 112 Gb/s (4-PAM) operation with $2.4mathbf{V}_{mathbf{pp}}$ output swing when the cascodes are used as linear broadband optical modulator drivers. The saturated output power, $pmb{P}_{mathbf{SAT}}$, of a single-ended stacked CMOS stage remains larger than 17 dBm from 1 to 45 GHz, with a peak of 19 dBm and PAE of 53.8% at 5.5 GHz, without any input and output matching network. A 4x MIMO transmitter with a differential version of the stacked CMOS output stage would meet the targeted 5G $pmb{P}_{mathbf{SAT}}$ of 28 dBm from 0.5 to 28 GHz. These results suggest that a single CMOS transceiver and PA could cover all the 5G bands from 0.5 GHz to 45 GHz. The n-MOSFET cascodes show better PAE above 10 GHz (33.4% at 28 GHz) than the CMOS version but with 1–2 dB lower $pmb{P}_{text{SAT}}$ and linearity.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123629533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8551054
S. Sirohi, V. Jain, Ajay Raman, B. T. Nukala, Elanchezhian Veeramani, J. Adkisson, A. Joseph
We present performance and ruggedness trade-offs for the different emitter widths of SiGe HBTs using GLOBALFOUNDRIES 1K5PAXE technology for power amplifier (PA) applications. The technology offers HBTs with low intrinsic base resistance (RBI) and low emitter-base capacitance $(mathbf{C}_{mathbf{BE}})$ which allows for wide emitter devices essential for high power density PA designs through improved emitter utilization. Load-pull measurements of HBTs with $mathbf{W}_{mathbf{E}}=1.2mu m$ show ~1.5dB higher gain at 5.8GHz for a ~17% smaller footprint compared to $text{W}_{text{E}}=0.8mu m$ HBT (for a fixed emitter area). However, smaller footprint increases thermal resistance which degrades ruggedness. Simulations show that the ruggedness can be recovered through power cell layout optimization or by using emitter ballasting techniques. This paper also shows the importance of good mutual heating model between devices for first pass design success and reduced design cycle time.
{"title":"Impact of Emitter Width Scaling on Performance and Ruggedness of SiGe HBTs for PA Applications","authors":"S. Sirohi, V. Jain, Ajay Raman, B. T. Nukala, Elanchezhian Veeramani, J. Adkisson, A. Joseph","doi":"10.1109/BCICTS.2018.8551054","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8551054","url":null,"abstract":"We present performance and ruggedness trade-offs for the different emitter widths of SiGe HBTs using GLOBALFOUNDRIES 1K5PAXE technology for power amplifier (PA) applications. The technology offers HBTs with low intrinsic base resistance (RBI) and low emitter-base capacitance $(mathbf{C}_{mathbf{BE}})$ which allows for wide emitter devices essential for high power density PA designs through improved emitter utilization. Load-pull measurements of HBTs with $mathbf{W}_{mathbf{E}}=1.2mu m$ show ~1.5dB higher gain at 5.8GHz for a ~17% smaller footprint compared to $text{W}_{text{E}}=0.8mu m$ HBT (for a fixed emitter area). However, smaller footprint increases thermal resistance which degrades ruggedness. Simulations show that the ruggedness can be recovered through power cell layout optimization or by using emitter ballasting techniques. This paper also shows the importance of good mutual heating model between devices for first pass design success and reduced design cycle time.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127703893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8551114
E. Jones, J. Poplawsky, Donavan Leonard, K. Chung, K. Mercurio, P. Brabant, T. Adam, P. Shea, T. Knight
We report on the use of atom probe tomography (APT), scanning transmission electron microscopy (STEM), and secondary ion mass spectroscopy (SIMS) to characterize doping profiles in the base region of SiGe HBT devices. We compare SIMS profiles obtained from large regions (400 um2) of the device wafer to profiles obtained from individual devices of different emitter window widths (0.25 and 0.18 um2) using APT. From this comparison we show how APT can provide a deeper insight into evaluating the fabrication process and its effects on electrical models of device performance and enabling the building of higher performance systems. We also demonstrate that APT can be used to characterize defects within the intrinsic regions of a device.
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