Pattern Generation for Post-Silicon Timing Validation Considering Power Supply Noise

Abstract

In this work, we address the problem of automatic test pattern generation for understanding circuit timing sensitivity to power supply noise (PSN) during post-silicon validation. Pseudo functional test patterns targeting the longest paths captured by each flip-flop are first generated. To determine the sensitivity to on-chip noise, the patterns are intelligently filled to achieve the desired PSN level. Our previous PSN control scheme is enhanced to consider both spatial and temporal information for better correlation with functional PSN. These patterns can be used to understand timing sensitivity in post-silicon validation by repeatedly applying the path delay test while sweeping the PSN experienced by the path from low to high.