This paper describes an innovative test approach to validate an anechoic Compact Range antenna indoor chamber. It documents the antenna chamber mmW characterization efforts and results for the Lockheed Martin Mission Systems & Training (MST) antenna chamber CR1 in Owego NY. The mmW characterization results indicate that the chamber amplitude performance is better than 0.8 dB RMS, and the chamber phase performance is better than 5 degree RMS. These errors are reasonably small compared with typical Electronic Support Measure (ESM) antenna calibration residual errors. Based on these characterization results, it is concluded that the Owego chamber CR1 is sufficient for mmW ESM antenna calibrations.
本文介绍了一种创新的消声紧凑距离天线室内室测试方法。它记录了洛·马任务系统与训练(MST)天线室CR1的天线室毫米波特性工作和结果。毫米波表征结果表明，腔幅值性能优于0.8 dB RMS，相位性能优于5度RMS。与典型的电子支撑测量(ESM)天线校准残差相比，这些误差相当小。基于这些表征结果，得出Owego腔室CR1足以用于毫米波ESM天线校准的结论。
{"title":"Innovative Antenna Chamber Characterization","authors":"T. Lam","doi":"10.1109/NATW.2014.13","DOIUrl":"https://doi.org/10.1109/NATW.2014.13","url":null,"abstract":"This paper describes an innovative test approach to validate an anechoic Compact Range antenna indoor chamber. It documents the antenna chamber mmW characterization efforts and results for the Lockheed Martin Mission Systems & Training (MST) antenna chamber CR1 in Owego NY. The mmW characterization results indicate that the chamber amplitude performance is better than 0.8 dB RMS, and the chamber phase performance is better than 5 degree RMS. These errors are reasonably small compared with typical Electronic Support Measure (ESM) antenna calibration residual errors. Based on these characterization results, it is concluded that the Owego chamber CR1 is sufficient for mmW ESM antenna calibrations.","PeriodicalId":283155,"journal":{"name":"2014 IEEE 23rd North Atlantic Test Workshop","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130417425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work presents a method to measure the frequency of an on-chip test clock in relation to a reference clock. Frequency measurement is accomplished by counting pulses of both test and reference clocks, albeit adjusting the reference clock pulse count to estimate the number of pulses that the test clock is expected to see. The proposed method places no constraints on the frequency relationship between the test and reference clocks which allows the reference clock frequency to be any multiple δ (1 <; δ ≤ 1) of the test clock frequency. Doing so allows a high degree of flexibility and a wide range of scenarios for which this approach could be deployed to measure the frequency of an unknown clock. Applications of this approach range from calibrating the frequency of on chip at speed test clocks for DFT, measurement of ppm of clocks subject to variations in process, temperature, spread spectrum effects among other considerations. The method also guarantees cycle to cycle accuracy in frequency measurement. Multiple on chips clocks can be tested using one instance of this method when the frequency information of all clocks to be tested is made available in specific register files.
{"title":"On-chip Clock Testing and Frequency Measurement","authors":"R. Tekumalla, Prakash Krishnamoorthy","doi":"10.1109/NATW.2014.12","DOIUrl":"https://doi.org/10.1109/NATW.2014.12","url":null,"abstract":"This work presents a method to measure the frequency of an on-chip test clock in relation to a reference clock. Frequency measurement is accomplished by counting pulses of both test and reference clocks, albeit adjusting the reference clock pulse count to estimate the number of pulses that the test clock is expected to see. The proposed method places no constraints on the frequency relationship between the test and reference clocks which allows the reference clock frequency to be any multiple δ (1 <; δ ≤ 1) of the test clock frequency. Doing so allows a high degree of flexibility and a wide range of scenarios for which this approach could be deployed to measure the frequency of an unknown clock. Applications of this approach range from calibrating the frequency of on chip at speed test clocks for DFT, measurement of ppm of clocks subject to variations in process, temperature, spread spectrum effects among other considerations. The method also guarantees cycle to cycle accuracy in frequency measurement. Multiple on chips clocks can be tested using one instance of this method when the frequency information of all clocks to be tested is made available in specific register files.","PeriodicalId":283155,"journal":{"name":"2014 IEEE 23rd North Atlantic Test Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115489284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A repairable memory cell consists of repair logic and a memory repair register (MRR) which holds the signature for memory repair. Every time a repairable memory is powered on, the memory repair register is programmed by transferring the memory repair signature from a nonvolatile memory such an EPROM into MRR. During repair signature programming, the MRR of all memories in the design are wired together to load the signature in a serial fashion. For example, if there are three memories in the design with an 8 bit MRR each, then each of these three MRR's will be configured to shift in a 24-bit signature in a serial fashion. During the course of normal operation, memories are frequently shutdown to reduce power consumption, while some part of the design remains operational. When these memories are powered back on, the MRR's must be reprogrammed for proper memory operation. This work provides an elegant mechanism to hold these MRR signatures in a shadow register which can later be used to reprogram the MRR to make the memories operational. The method provides a mechanism for loading each of the memories' MRR's in parallel, allowing faster system bring up.
{"title":"Local Repair Signature Handling for Repairable Memories","authors":"R. Tekumalla, Prakash Krishnamoorthy","doi":"10.1109/NATW.2014.10","DOIUrl":"https://doi.org/10.1109/NATW.2014.10","url":null,"abstract":"A repairable memory cell consists of repair logic and a memory repair register (MRR) which holds the signature for memory repair. Every time a repairable memory is powered on, the memory repair register is programmed by transferring the memory repair signature from a nonvolatile memory such an EPROM into MRR. During repair signature programming, the MRR of all memories in the design are wired together to load the signature in a serial fashion. For example, if there are three memories in the design with an 8 bit MRR each, then each of these three MRR's will be configured to shift in a 24-bit signature in a serial fashion. During the course of normal operation, memories are frequently shutdown to reduce power consumption, while some part of the design remains operational. When these memories are powered back on, the MRR's must be reprogrammed for proper memory operation. This work provides an elegant mechanism to hold these MRR signatures in a shadow register which can later be used to reprogram the MRR to make the memories operational. The method provides a mechanism for loading each of the memories' MRR's in parallel, allowing faster system bring up.","PeriodicalId":283155,"journal":{"name":"2014 IEEE 23rd North Atlantic Test Workshop","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123069809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Aymen Touati, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, P. Bernardi
This paper presents an evaluation framework for functional programs. Programs are evaluated w.r.t. functional and structural metrics. The goal is to verify if the targeted functional programs can be re-used for verification and test purposes.
{"title":"A Comprehensive Evaluation of Functional Programs for Power-Aware Test","authors":"Aymen Touati, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, P. Bernardi","doi":"10.1109/NATW.2014.23","DOIUrl":"https://doi.org/10.1109/NATW.2014.23","url":null,"abstract":"This paper presents an evaluation framework for functional programs. Programs are evaluated w.r.t. functional and structural metrics. The goal is to verify if the targeted functional programs can be re-used for verification and test purposes.","PeriodicalId":283155,"journal":{"name":"2014 IEEE 23rd North Atlantic Test Workshop","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127985013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Memories from the Library vendor come as a hard macro in the design. With the increased focus on meeting timing requirements, memories are provided in an integrated form from vendor. These integrated memory hard macros not only consist of SRAM read-write behavior but also comprise of scan chains and bypass logic around SRAM. This bypass logic consists of shadow cells which are already stitched into small scan chains inside the hard macro. Since this whole memory bypass and shadow logic is inside hard macro, it can be treated as a separate timing closed module in the design. Because of the separate timing closure process, there can be an occurrence of timing violation during silicon test on the logic interface between the SoC and the hard macro. There is a need to have an optional mode where designer should have freedom to generate the patterns with or without consideration of the capture mode of the memory scan cells. In this paper, we present a methodology to handle memory scan chains by controlling the memory clock during capture, using a combination of control signals which already exist in the design.
{"title":"On Handling Memory Scan Chains","authors":"Surbhi Bansal, Aviansh Mendhalkar, R. Tekumalla","doi":"10.1109/NATW.2014.11","DOIUrl":"https://doi.org/10.1109/NATW.2014.11","url":null,"abstract":"Memories from the Library vendor come as a hard macro in the design. With the increased focus on meeting timing requirements, memories are provided in an integrated form from vendor. These integrated memory hard macros not only consist of SRAM read-write behavior but also comprise of scan chains and bypass logic around SRAM. This bypass logic consists of shadow cells which are already stitched into small scan chains inside the hard macro. Since this whole memory bypass and shadow logic is inside hard macro, it can be treated as a separate timing closed module in the design. Because of the separate timing closure process, there can be an occurrence of timing violation during silicon test on the logic interface between the SoC and the hard macro. There is a need to have an optional mode where designer should have freedom to generate the patterns with or without consideration of the capture mode of the memory scan cells. In this paper, we present a methodology to handle memory scan chains by controlling the memory clock during capture, using a combination of control signals which already exist in the design.","PeriodicalId":283155,"journal":{"name":"2014 IEEE 23rd North Atlantic Test Workshop","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126187094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yu Huang, M. Kassab, J. Jahangiri, J. Rajski, Wu-Tung Cheng, Dongkwan Han, Jihye Kim, K. Chung
This paper proposes an innovative test compression technology for system-on-chip (SoC) designs to share scan input channels across multiple cores which use EDT [1] compression. A new DFT compression architecture is proposed to separate control and data channels such that the control channels can be individually accessible, whereas data channels can be shared among a group of cores. The paper illustrates the benefits of the proposed technology in both the enhancement of compression ratios and the flexibility of test compression planning in a core-based SoC design flow. Experimental results with a few large industrial SoCs demonstrate that using the proposed technology the compression can be improved up to 1.87X.
{"title":"Test Compression Improvement with EDT Channel Sharing in SoC Designs","authors":"Yu Huang, M. Kassab, J. Jahangiri, J. Rajski, Wu-Tung Cheng, Dongkwan Han, Jihye Kim, K. Chung","doi":"10.1109/NATW.2014.14","DOIUrl":"https://doi.org/10.1109/NATW.2014.14","url":null,"abstract":"This paper proposes an innovative test compression technology for system-on-chip (SoC) designs to share scan input channels across multiple cores which use EDT [1] compression. A new DFT compression architecture is proposed to separate control and data channels such that the control channels can be individually accessible, whereas data channels can be shared among a group of cores. The paper illustrates the benefits of the proposed technology in both the enhancement of compression ratios and the flexibility of test compression planning in a core-based SoC design flow. Experimental results with a few large industrial SoCs demonstrate that using the proposed technology the compression can be improved up to 1.87X.","PeriodicalId":283155,"journal":{"name":"2014 IEEE 23rd North Atlantic Test Workshop","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131586434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, we address the problem of automatic test pattern generation for understanding circuit timing sensitivity to power supply noise (PSN) during post-silicon validation. Pseudo functional test patterns targeting the longest paths captured by each flip-flop are first generated. To determine the sensitivity to on-chip noise, the patterns are intelligently filled to achieve the desired PSN level. Our previous PSN control scheme is enhanced to consider both spatial and temporal information for better correlation with functional PSN. These patterns can be used to understand timing sensitivity in post-silicon validation by repeatedly applying the path delay test while sweeping the PSN experienced by the path from low to high.
{"title":"Pattern Generation for Post-Silicon Timing Validation Considering Power Supply Noise","authors":"Tengteng Zhang, Yukun Gao, D. Walker","doi":"10.1109/NATW.2014.21","DOIUrl":"https://doi.org/10.1109/NATW.2014.21","url":null,"abstract":"In this work, we address the problem of automatic test pattern generation for understanding circuit timing sensitivity to power supply noise (PSN) during post-silicon validation. Pseudo functional test patterns targeting the longest paths captured by each flip-flop are first generated. To determine the sensitivity to on-chip noise, the patterns are intelligently filled to achieve the desired PSN level. Our previous PSN control scheme is enhanced to consider both spatial and temporal information for better correlation with functional PSN. These patterns can be used to understand timing sensitivity in post-silicon validation by repeatedly applying the path delay test while sweeping the PSN experienced by the path from low to high.","PeriodicalId":283155,"journal":{"name":"2014 IEEE 23rd North Atlantic Test Workshop","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121803286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a new adaptive computing fabric (ACF) that achieves both real-time multi-mode/multi-rate adaptation and lower error floor for cognitive SoC applications is presented. The VLSI architecture of the ACF is experimentally shown to meet the DVB, 802.3an and 802.ad target specifications. Our design delivers a 10-14 bit error rate (BER) with a bit energyto- noise density of Eb/N0=5dB with an energy-efficiency of 0.61pJ/bit. Experiments are conducted comparing Low-Density Parity-Check (LDPC) codes error correction performance in the presence of unreliable circuits due to aggressive manufacturing defect rates and/or run-time defect rates from components enabled by SoC integration. We report on a 201.6Gbps 65nm CMOS design and Xilinx FPGA prototype, which demonstrates in hardware how real-time adaptive techniques can accelerate decoding convergence and lower the error floor. Finally, We show experimentally that our ACF design can achieve energyefficiency throughput speed-ups at scale in the range of 200x to 5000x as compared to the same algorithm running in software (optimized C program) on a single CPU core.
{"title":"Design and Test of Adaptive Computing Fabrics for Scalable and High-Efficiency Cognitive SoC Applications","authors":"P. Nsame, G. Bois, Y. Savaria","doi":"10.1109/NATW.2014.18","DOIUrl":"https://doi.org/10.1109/NATW.2014.18","url":null,"abstract":"In this paper, a new adaptive computing fabric (ACF) that achieves both real-time multi-mode/multi-rate adaptation and lower error floor for cognitive SoC applications is presented. The VLSI architecture of the ACF is experimentally shown to meet the DVB, 802.3an and 802.ad target specifications. Our design delivers a 10-14 bit error rate (BER) with a bit energyto- noise density of Eb/N0=5dB with an energy-efficiency of 0.61pJ/bit. Experiments are conducted comparing Low-Density Parity-Check (LDPC) codes error correction performance in the presence of unreliable circuits due to aggressive manufacturing defect rates and/or run-time defect rates from components enabled by SoC integration. We report on a 201.6Gbps 65nm CMOS design and Xilinx FPGA prototype, which demonstrates in hardware how real-time adaptive techniques can accelerate decoding convergence and lower the error floor. Finally, We show experimentally that our ACF design can achieve energyefficiency throughput speed-ups at scale in the range of 200x to 5000x as compared to the same algorithm running in software (optimized C program) on a single CPU core.","PeriodicalId":283155,"journal":{"name":"2014 IEEE 23rd North Atlantic Test Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130874534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An aperiodic test clock methodology to reduce test time of wafer sort has been recently proposed. In practice, however, an automatic test equipment (ATE) allows only a small number of clock periods and finding those is a mathematically complex problem. This paper proposes an algorithm for optimal selection of any given number of tester clock periods.
{"title":"Optimal Selection of ATE Frequencies for Test Time Reduction Using Aperiodic Clock","authors":"S. Gunasekar, V. Agrawal","doi":"10.1109/NATW.2014.19","DOIUrl":"https://doi.org/10.1109/NATW.2014.19","url":null,"abstract":"An aperiodic test clock methodology to reduce test time of wafer sort has been recently proposed. In practice, however, an automatic test equipment (ATE) allows only a small number of clock periods and finding those is a mathematically complex problem. This paper proposes an algorithm for optimal selection of any given number of tester clock periods.","PeriodicalId":283155,"journal":{"name":"2014 IEEE 23rd North Atlantic Test Workshop","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127848751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper describes asynchronous fault detection in silicon chips with network of embedded instruments based on IEEE P1687 IJTAG. This technique allows faster fault detection and localization by using asynchronous signal propagation from instruments to instrumentation network controller. The additional hardware is described, scenarios of operation including multiple simultaneous fault detection and localization are analysed.
{"title":"Asynchronous Fault Detection in IEEE P1687 Instrument Network","authors":"K. Shibin, S. Devadze, A. Jutman","doi":"10.1109/NATW.2014.24","DOIUrl":"https://doi.org/10.1109/NATW.2014.24","url":null,"abstract":"The paper describes asynchronous fault detection in silicon chips with network of embedded instruments based on IEEE P1687 IJTAG. This technique allows faster fault detection and localization by using asynchronous signal propagation from instruments to instrumentation network controller. The additional hardware is described, scenarios of operation including multiple simultaneous fault detection and localization are analysed.","PeriodicalId":283155,"journal":{"name":"2014 IEEE 23rd North Atlantic Test Workshop","volume":"271 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122758549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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