Programmable pacing channel with a fully on-chip LDO regulator for cardiac pacemaker

Chih-Jen Cheng, Chung-Jui Wu, Shuenn-Yuh Lee
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引用次数: 21

Abstract

A novel dual-voltage pacing system for implant pacemaker is presented in this paper. In order to reduce supply voltage ripple and diminish process variation imposed on the divided-resistor, a fully on-chip low-dropout (LDO) regulator is proposed. Meanwhile, the adjustable pacing circuit together with a sense feedback is employed to deliver electrical stimuli of 16-step amplitudes to induce cardiac contraction. The pacing circuit with a LDO regulator was fabricated in TSMC 0.35-mum CMOS technology, consuming total power of 1.29 muW including 185 nA of ground current in 1.2-V LDO and having a power consumption of 30 nW in the 1-V pacing step controller. Experimental results demonstrate that the proposed LDO regulator features a power-supply rejection ratio (PSRR) of -30 dB with the output ripple of 570 muVpp under the input sinusoidal wave of 19.6 mVpp. Even with the load current up to 10 muA, LDO yields a line regulation that is less than 3% deviation.
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可编程起搏通道与一个完全在芯片上的LDO调节器心脏起搏器
介绍了一种新型的双电压起搏系统。为了减小电源电压纹波和减小施加在分路电阻上的工艺变化,提出了一种全片上低差(LDO)稳压器。同时,利用可调节的起搏电路和感觉反馈,传递16阶振幅的电刺激,诱导心脏收缩。采用台积电0.35 μ m CMOS工艺制作了带LDO稳压器的起搏器电路,其中1.2 v LDO的接地电流为185 nA, 1 v起搏器步进控制器的功耗为30 nW,总功耗为1.29 muW。实验结果表明,在输入正弦波为19.6 mVpp的情况下,LDO稳压器的电源抑制比(PSRR)为-30 dB,输出纹波为570 muVpp。即使负载电流高达10mua, LDO也能产生小于3%偏差的线路调节。
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