F. Arnaud, S. Haendler, S. Clerc, R. Ranica, A. Gandolfo, O. Weber
{"title":"28nm FDSOI Platform with Embedded PCM for IoT, ULP, Digital, Analog, Automotive and others Applications","authors":"F. Arnaud, S. Haendler, S. Clerc, R. Ranica, A. Gandolfo, O. Weber","doi":"10.1109/ESSCIRC.2019.8902913","DOIUrl":null,"url":null,"abstract":"This paper proposes a general overview of Fully Depleted Silicon On Insulator (FDSOI) technology advantages leveraging body bias capability as a key enabler for digital, analog and memories performance enhancement. 2x total power contraction for digital designs has been demonstrating without any frequency degradation thanks to Forward Body Biasing (FBB), combined with 70% transistor variability reduction. Power of analog blocks has been strongly reduced with body bias technique while keeping trans-conductance efficiency increasing and output voltage gain. Finally, excellent memories performances has been achieved by applying FBB/RBB solution, dropping the leakage of unselected word-line in Phase Change Memory (PCM) array and improving Vmin operation for static RAM across a wide temperature range.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2019.8902913","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper proposes a general overview of Fully Depleted Silicon On Insulator (FDSOI) technology advantages leveraging body bias capability as a key enabler for digital, analog and memories performance enhancement. 2x total power contraction for digital designs has been demonstrating without any frequency degradation thanks to Forward Body Biasing (FBB), combined with 70% transistor variability reduction. Power of analog blocks has been strongly reduced with body bias technique while keeping trans-conductance efficiency increasing and output voltage gain. Finally, excellent memories performances has been achieved by applying FBB/RBB solution, dropping the leakage of unselected word-line in Phase Change Memory (PCM) array and improving Vmin operation for static RAM across a wide temperature range.