Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902814
Xi Yang, Seung-Jun Bae, Hae-Seung Lee
An 8-bit 2.8 GS/s flash ADC with time-based offset calibration and interpolation is realized in 65 nm CMOS. The proposed time-based offset calibration uses intentional timing skew for offset cancellation without adding extra load to comparators, thus avoiding the speed penalty. The time-based 4x interpolation reduces the number of comparators to 1/4 and provides calibration capability for 8-bit accuracy through SR latches and delay lines. At 2.8 GS/s, the prototype consumes 51 mW from a 1-V supply and achieves Nyquist SNDR of 43.3 dB, effective resolution bandwidth (ERBW) of 1.52 GHz, and Walden figure-of-merit (FoM) of 153 fJ/conv-step, reporting a higher Nyquist ENOB than state-of-the-art single-channel flash ADCs with comparable FoM.
{"title":"An 8-bit 2.8 GS/s Flash ADC with Time-based Offset Calibration and Interpolation in 65 nm CMOS","authors":"Xi Yang, Seung-Jun Bae, Hae-Seung Lee","doi":"10.1109/ESSCIRC.2019.8902814","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902814","url":null,"abstract":"An 8-bit 2.8 GS/s flash ADC with time-based offset calibration and interpolation is realized in 65 nm CMOS. The proposed time-based offset calibration uses intentional timing skew for offset cancellation without adding extra load to comparators, thus avoiding the speed penalty. The time-based 4x interpolation reduces the number of comparators to 1/4 and provides calibration capability for 8-bit accuracy through SR latches and delay lines. At 2.8 GS/s, the prototype consumes 51 mW from a 1-V supply and achieves Nyquist SNDR of 43.3 dB, effective resolution bandwidth (ERBW) of 1.52 GHz, and Walden figure-of-merit (FoM) of 153 fJ/conv-step, reporting a higher Nyquist ENOB than state-of-the-art single-channel flash ADCs with comparable FoM.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115587076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902907
Jacob Goeppert, Simon Braun, David Pellhammer, Mohammad Amayreh, J. Leicht, M. Keller, Y. Manoli
This paper presents a power management unit for a multi-source single-load system for thermoelectric energy harvesting. The system uses a conventional two-converter architecture and a time multiplexed hysteretic control scheme. The output voltage of four µTEGs with an open circuit voltage from 3 V to 5 V and an internal resistance of 2 kΩ to 8 kΩ are controlled into their respective maximum power point at a maximum measured tracking loss of 2.88 %. Tight system area design constraints require a high degree of integration and the use of a switched capacitor converter as well as an integrated low-dropout regulator. The system achieves a peak end-to-end efficiency of 37.7 % at the maximum input power of 4.44 mW. (Keywords: low power, power management, µTEG, micro energy harvesting)
{"title":"Area Constrained Multi-Source Power Management for Thermoelectric Energy Harvesting","authors":"Jacob Goeppert, Simon Braun, David Pellhammer, Mohammad Amayreh, J. Leicht, M. Keller, Y. Manoli","doi":"10.1109/ESSCIRC.2019.8902907","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902907","url":null,"abstract":"This paper presents a power management unit for a multi-source single-load system for thermoelectric energy harvesting. The system uses a conventional two-converter architecture and a time multiplexed hysteretic control scheme. The output voltage of four µTEGs with an open circuit voltage from 3 V to 5 V and an internal resistance of 2 kΩ to 8 kΩ are controlled into their respective maximum power point at a maximum measured tracking loss of 2.88 %. Tight system area design constraints require a high degree of integration and the use of a switched capacitor converter as well as an integrated low-dropout regulator. The system achieves a peak end-to-end efficiency of 37.7 % at the maximum input power of 4.44 mW. (Keywords: low power, power management, µTEG, micro energy harvesting)","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"458 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124257797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902622
R. Giterman, Maoz Wicentowski, Oron Chertkow, I. Sever, Ishai Kehati, Y. Weizman, O. Keren, A. Fish
Power analysis attacks are an effective tool to extract sensitive information using side-channel analysis, forming a serious threat to IoT systems-on-a-chip (SoCs). Embedded memories implemented with conventional 6T SRAM macrocells often dominate the area and power of these SoCs. In this paper, for the first time, we use silicon measurements to prove that conventional SRAM arrays leak valuable information and that their data can be extracted using power analysis attacks. In order to provide a power analysis resilient embedded memory and adhere to the area constraints of modern SoCs, we implement a low-cost impedance randomization unit, which is integrated into the periphery of a conventional 6T SRAM macro. Preliminary silicon measurements of a 55 nm test-chip implementing the proposed memory array demonstrate a significant information leakage reduction at a low-cost 1% area overhead and no speed and power penalties compared to a conventional SRAM design.
{"title":"Power Analysis Resilient SRAM Design Implemented with a 1% Area Overhead Impedance Randomization Unit for Security Applications","authors":"R. Giterman, Maoz Wicentowski, Oron Chertkow, I. Sever, Ishai Kehati, Y. Weizman, O. Keren, A. Fish","doi":"10.1109/ESSCIRC.2019.8902622","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902622","url":null,"abstract":"Power analysis attacks are an effective tool to extract sensitive information using side-channel analysis, forming a serious threat to IoT systems-on-a-chip (SoCs). Embedded memories implemented with conventional 6T SRAM macrocells often dominate the area and power of these SoCs. In this paper, for the first time, we use silicon measurements to prove that conventional SRAM arrays leak valuable information and that their data can be extracted using power analysis attacks. In order to provide a power analysis resilient embedded memory and adhere to the area constraints of modern SoCs, we implement a low-cost impedance randomization unit, which is integrated into the periphery of a conventional 6T SRAM macro. Preliminary silicon measurements of a 55 nm test-chip implementing the proposed memory array demonstrate a significant information leakage reduction at a low-cost 1% area overhead and no speed and power penalties compared to a conventional SRAM design.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"201 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123732707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902906
P. Fan, Anand Savanth, Benoît Labbé, Pranay Prabhat, James Myers
The lower bound on the power expended by an RC relaxation oscillator is decided by the RC network. This can be minimized by reducing the oscillation swing and increasing R. In the former technique, tighter comparator constraints limit power benefits while the latter technique increases resistor thermal noise bounding long-term jitter. To this end, this letter presents a fully integrated RC oscillator with core voltage aggressively scaled to subthreshold levels. A self-clocked switched-capacitor network is used to minimize voltage drop-out power loss. Full forward-body-biasing technique helps reduce device on-resistance. Additionally, temperature coefficient compensation for time constant is accomplished by poly resistors and a VTH-tracking reference scheme which avoids the use of diffusion resistors. This design is silicon-proven on 65-nm CMOS (0.0356-mm2 area). The implementation has a 33-kHz clock with 32.2 nW at 1.2 V. Line sensitivity is within +0.7/−0.6% per volt across 16 samples for 1 to 1.5 V. Temperature sensitivity was measured to be 56 ppm/°C from 0 °C to 85 °C and measured Allan deviation <100 ppm for averaging interval of τ = 400 s and <40 ppm for τ = 3000 s.
{"title":"A 0.98-nW/kHz 33-kHz Fully Integrated Subthreshold-Region Operation RC Oscillator With Forward-Body-Biasing","authors":"P. Fan, Anand Savanth, Benoît Labbé, Pranay Prabhat, James Myers","doi":"10.1109/ESSCIRC.2019.8902906","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902906","url":null,"abstract":"The lower bound on the power expended by an RC relaxation oscillator is decided by the RC network. This can be minimized by reducing the oscillation swing and increasing R. In the former technique, tighter comparator constraints limit power benefits while the latter technique increases resistor thermal noise bounding long-term jitter. To this end, this letter presents a fully integrated RC oscillator with core voltage aggressively scaled to subthreshold levels. A self-clocked switched-capacitor network is used to minimize voltage drop-out power loss. Full forward-body-biasing technique helps reduce device on-resistance. Additionally, temperature coefficient compensation for time constant is accomplished by poly resistors and a VTH-tracking reference scheme which avoids the use of diffusion resistors. This design is silicon-proven on 65-nm CMOS (0.0356-mm2 area). The implementation has a 33-kHz clock with 32.2 nW at 1.2 V. Line sensitivity is within +0.7/−0.6% per volt across 16 samples for 1 to 1.5 V. Temperature sensitivity was measured to be 56 ppm/°C from 0 °C to 85 °C and measured Allan deviation <100 ppm for averaging interval of τ = 400 s and <40 ppm for τ = 3000 s.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128512387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902873
Tianli Zhang, Yuefeng Cao, Shumin Zhang, Chixiao Chen, Fan Ye, Junyan Ren
The paper presents a machine-learning based calibration scheme for split pipelined-SAR ADCs with open-loop residual amplifiers. Different from conventional methods, the proposed scheme is prior-knowledge-free. The scheme adopts a two-layer neural network, and directly uses the bit-wise comparator results as inputs. The neural network compensates the distortion and can be compressed by 75% due to the network’s sparsity. A 14-bit 60-MSps split pipelined-SAR ADC with gain boosted dynamic amplifiers is fabricated in 28nm CMOS to validate the scheme. The measurement results show the ADC achieves an SFDR of 93.7 dB and an ENOB of 10.7b, consuming 2.79 mW. To the authors’ knowledge, it achieves the best SFDR among Nyquist ADCs with open-loop amplifiers.
{"title":"Machine Learning Based Prior-Knowledge-Free Calibration for Split Pipelined-SAR ADCs with Open-Loop Amplifiers Achieving 93.7-dB SFDR","authors":"Tianli Zhang, Yuefeng Cao, Shumin Zhang, Chixiao Chen, Fan Ye, Junyan Ren","doi":"10.1109/ESSCIRC.2019.8902873","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902873","url":null,"abstract":"The paper presents a machine-learning based calibration scheme for split pipelined-SAR ADCs with open-loop residual amplifiers. Different from conventional methods, the proposed scheme is prior-knowledge-free. The scheme adopts a two-layer neural network, and directly uses the bit-wise comparator results as inputs. The neural network compensates the distortion and can be compressed by 75% due to the network’s sparsity. A 14-bit 60-MSps split pipelined-SAR ADC with gain boosted dynamic amplifiers is fabricated in 28nm CMOS to validate the scheme. The measurement results show the ADC achieves an SFDR of 93.7 dB and an ENOB of 10.7b, consuming 2.79 mW. To the authors’ knowledge, it achieves the best SFDR among Nyquist ADCs with open-loop amplifiers.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114839355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902797
Roland Van Wegberg, J. Penders, C. Hoof, N. V. Helleputte, W. Sijbers, Shuang Song, Arjan Breeschoten, P. Vis, M. Konijnenburg, Hui Jiang, M. Rooijakkers, T. Berset
This letter presents a 5-channel unipolar fetal electrocardiogram readout IC for monitoring the health of a fetus during pregnancy. Each readout channel includes an instrumentation amplifier, a programable gain amplifier and a successive approximation register ADC. A unipolar, common half branch reuse topology is used to achieve low noise, low power, low crosstalk between the channels high input impedance and high CMRR at the same time. Each channel achieves an input referred noise of 0.47 µVrms in 0.5 to 150 Hz, while consuming a power of 43.2 µW. The 5-channel system provides a CMRR of 98 dB and an interchannel crosstalk rejection of 95 dB. The chip is implemented in a standard 55-nm CMOS process and occupies an area of 4.0 mm2. The whole chip, including five readout channels, leadoff detection, reference generation, autonomous data acquisition with on-chip sample storage and an interrupt-based serial peripheral host interface consumes a total power of 258 µW.
{"title":"A 5-Channel Unipolar Fetal-ECG Readout IC for Patch-Based Fetal Monitoring","authors":"Roland Van Wegberg, J. Penders, C. Hoof, N. V. Helleputte, W. Sijbers, Shuang Song, Arjan Breeschoten, P. Vis, M. Konijnenburg, Hui Jiang, M. Rooijakkers, T. Berset","doi":"10.1109/ESSCIRC.2019.8902797","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902797","url":null,"abstract":"This letter presents a 5-channel unipolar fetal electrocardiogram readout IC for monitoring the health of a fetus during pregnancy. Each readout channel includes an instrumentation amplifier, a programable gain amplifier and a successive approximation register ADC. A unipolar, common half branch reuse topology is used to achieve low noise, low power, low crosstalk between the channels high input impedance and high CMRR at the same time. Each channel achieves an input referred noise of 0.47 µVrms in 0.5 to 150 Hz, while consuming a power of 43.2 µW. The 5-channel system provides a CMRR of 98 dB and an interchannel crosstalk rejection of 95 dB. The chip is implemented in a standard 55-nm CMOS process and occupies an area of 4.0 mm2. The whole chip, including five readout channels, leadoff detection, reference generation, autonomous data acquisition with on-chip sample storage and an interrupt-based serial peripheral host interface consumes a total power of 258 µW.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125708919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902612
Van Loi Le, Taegeun Yoo, Ju Eon Kim, K. Baek, T. T. Kim
This letter presents a low-power motion gesture recognition system-on-chip (SoC) for smart devices. The SoC incorporates a low-power image sensor and a memory-efficient outermost-edge-based gesture sensing DSP. The DSP utilizes a self-adaptive motion detector that automatically updates a motion-pixel threshold for accurately sensing hand movements. A convolution-based noise-tolerant feature extraction (FE) technique is also developed for preventing detection errors caused by random noises in the images from the low-power sensor. The FE architecture is highly accelerated utilizing parallelisms and pipelining for achieving low-latency real-time gesture recognition. Measurements from a test chip fabricated in 65-nm CMOS show that the SoC consumes 213.7 µW with only 3-µW dynamic power at 30 f/s. The SoC occupies only 0.54 mm2, making it well applicable for wearable devices and sensor nodes. The image sensor is fully operational down to 0.6 V while the DSP can be scaled down to 0.46 V. The average recognition accuracy of the system is 85% while the latency is 1.056 ms.
{"title":"A 213.7-µW Gesture Sensing System-On-Chip With Self-Adaptive Motion Detection and Noise-Tolerant Outermost-Edge-Based Feature Extraction in 65 nm","authors":"Van Loi Le, Taegeun Yoo, Ju Eon Kim, K. Baek, T. T. Kim","doi":"10.1109/ESSCIRC.2019.8902612","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902612","url":null,"abstract":"This letter presents a low-power motion gesture recognition system-on-chip (SoC) for smart devices. The SoC incorporates a low-power image sensor and a memory-efficient outermost-edge-based gesture sensing DSP. The DSP utilizes a self-adaptive motion detector that automatically updates a motion-pixel threshold for accurately sensing hand movements. A convolution-based noise-tolerant feature extraction (FE) technique is also developed for preventing detection errors caused by random noises in the images from the low-power sensor. The FE architecture is highly accelerated utilizing parallelisms and pipelining for achieving low-latency real-time gesture recognition. Measurements from a test chip fabricated in 65-nm CMOS show that the SoC consumes 213.7 µW with only 3-µW dynamic power at 30 f/s. The SoC occupies only 0.54 mm2, making it well applicable for wearable devices and sensor nodes. The image sensor is fully operational down to 0.6 V while the DSP can be scaled down to 0.46 V. The average recognition accuracy of the system is 85% while the latency is 1.056 ms.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133579540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902832
Jeffrey Abbott, Tianyang Ye, Hongkun Park, D. Ham
CMOS technology and its Moore’s Law scaling is an enormously successful technology paradigm that has continued to transform our computation and communication abilities. Outside the applications in computation and communication, CMOS technology has been increasingly applied to the life sciences, with a wealth of silicon integrated circuits developed to interface with biological molecules and cells. Concretely, large-scale arrays of active electrodes are integrated using CMOS technology for highly parallel electronic detection of biomolecular/ionic charges and cellular potentials for DNA sequencing, molecular diagnostics, and electrophysiology. Parallelism enabled by CMOS scalability is well suited to process the big data in these biotechnological applications. Here we offer a brief review on these CMOS-bio interfaces, while the corresponding presentation will focus on a sub-topic of CMOS electrophysiology with mammalian neurons.
{"title":"CMOS interface with biological molecules and cells","authors":"Jeffrey Abbott, Tianyang Ye, Hongkun Park, D. Ham","doi":"10.1109/ESSCIRC.2019.8902832","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902832","url":null,"abstract":"CMOS technology and its Moore’s Law scaling is an enormously successful technology paradigm that has continued to transform our computation and communication abilities. Outside the applications in computation and communication, CMOS technology has been increasingly applied to the life sciences, with a wealth of silicon integrated circuits developed to interface with biological molecules and cells. Concretely, large-scale arrays of active electrodes are integrated using CMOS technology for highly parallel electronic detection of biomolecular/ionic charges and cellular potentials for DNA sequencing, molecular diagnostics, and electrophysiology. Parallelism enabled by CMOS scalability is well suited to process the big data in these biotechnological applications. Here we offer a brief review on these CMOS-bio interfaces, while the corresponding presentation will focus on a sub-topic of CMOS electrophysiology with mammalian neurons.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133636682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902876
Mingliang Tan, E. Kang, Jae-Sung An, Z. Chang, P. Vince, N. Sénégond, M. Pertijs
This letter presents a compact programmable high-voltage (HV) pulser for ultrasound imaging, designed for driving capacitive micromachined ultrasonic transducers (CMUTs) in miniature ultrasound probes. To enable bipolar return-to-zero (RZ) pulsing and embedded transmit/receive switching, a compact back-to-back isolating HV switch is proposed that employs HV floating-gate drivers with only one HV MOS transistor each. The pulser can be digitally programmed to generate bipolar pulses with and without RZ, with a peak-to-peak swing up to 60 V, as well as negative and positive unipolar pulses. It can generate bursts of up to 63 pulses, with a maximum pulse frequency of 9 MHz for an 18-pF transducer capacitance. Realized in TSMC 0.18-µm HV BCD technology, the pulser occupies only 0.167 mm2. Electrical characterization results of the pulser, as well as acoustic results obtained in the combination with a 7.5-MHz CMUT transducer, are presented.
{"title":"An Integrated Programmable High-Voltage Bipolar Pulser With Embedded Transmit/Receive Switch for Miniature Ultrasound Probes","authors":"Mingliang Tan, E. Kang, Jae-Sung An, Z. Chang, P. Vince, N. Sénégond, M. Pertijs","doi":"10.1109/ESSCIRC.2019.8902876","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902876","url":null,"abstract":"This letter presents a compact programmable high-voltage (HV) pulser for ultrasound imaging, designed for driving capacitive micromachined ultrasonic transducers (CMUTs) in miniature ultrasound probes. To enable bipolar return-to-zero (RZ) pulsing and embedded transmit/receive switching, a compact back-to-back isolating HV switch is proposed that employs HV floating-gate drivers with only one HV MOS transistor each. The pulser can be digitally programmed to generate bipolar pulses with and without RZ, with a peak-to-peak swing up to 60 V, as well as negative and positive unipolar pulses. It can generate bursts of up to 63 pulses, with a maximum pulse frequency of 9 MHz for an 18-pF transducer capacitance. Realized in TSMC 0.18-µm HV BCD technology, the pulser occupies only 0.167 mm2. Electrical characterization results of the pulser, as well as acoustic results obtained in the combination with a 7.5-MHz CMUT transducer, are presented.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114612247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902549
Farhad Bozorgi, M. Bruccoleri, M. Repossi, E. Temporiti, A. Mazzanti, F. Svelto
This letter presents a 3-D-integrated 26 Gb/s opto-electrical receiver front-end. The electronic integrated circuit (EIC) is fabricated in a BiCMOS-55-nm technology, flipped and placed on top of the photonic integrated circuits (PICs) die through copper pillars. In the receiver chain, a fully differential shunt-feedback TI amplifier (FD-SF TIA) is followed by a limiting amplifiers (LAs) with embedded equalization, output driver and an automatic offset cancelation loop. The whole receiver provides a transimpedance (TI) gain of 76 dBñ with 30-GHz bandwidth. By exploiting the FD-SF TIA with low parasitic capacitance of the Germanium dual heterojunction photo diode (Ge-PD) in the photonic die, the receiver achieves sensitivity of −15.2 dBm optical modulation amplitude (OMA) at Ge-PD and −10-dBm OMA at the single-mode fiber (SMF) optical output with bit error rate of 10−12 and PRBS 15. The sensitivity is aligned with state-of-the-art receivers employing discrete photonics and, to author’s best knowledge, it is the lowest reported among published 25 Gb/s receivers exploiting silicon photonics.
{"title":"A 26-Gb/s 3-D-Integrated Silicon Photonic Receiver in BiCMOS-55 nm and PIC25G With – 15.2-dBm OMA Sensitivity","authors":"Farhad Bozorgi, M. Bruccoleri, M. Repossi, E. Temporiti, A. Mazzanti, F. Svelto","doi":"10.1109/ESSCIRC.2019.8902549","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902549","url":null,"abstract":"This letter presents a 3-D-integrated 26 Gb/s opto-electrical receiver front-end. The electronic integrated circuit (EIC) is fabricated in a BiCMOS-55-nm technology, flipped and placed on top of the photonic integrated circuits (PICs) die through copper pillars. In the receiver chain, a fully differential shunt-feedback TI amplifier (FD-SF TIA) is followed by a limiting amplifiers (LAs) with embedded equalization, output driver and an automatic offset cancelation loop. The whole receiver provides a transimpedance (TI) gain of 76 dBñ with 30-GHz bandwidth. By exploiting the FD-SF TIA with low parasitic capacitance of the Germanium dual heterojunction photo diode (Ge-PD) in the photonic die, the receiver achieves sensitivity of −15.2 dBm optical modulation amplitude (OMA) at Ge-PD and −10-dBm OMA at the single-mode fiber (SMF) optical output with bit error rate of 10−12 and PRBS 15. The sensitivity is aligned with state-of-the-art receivers employing discrete photonics and, to author’s best knowledge, it is the lowest reported among published 25 Gb/s receivers exploiting silicon photonics.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129551192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}