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ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)最新文献

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An 8-bit 2.8 GS/s Flash ADC with Time-based Offset Calibration and Interpolation in 65 nm CMOS 基于时间偏移校准和插值的8位2.8 GS/s Flash ADC
Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902814
Xi Yang, Seung-Jun Bae, Hae-Seung Lee
An 8-bit 2.8 GS/s flash ADC with time-based offset calibration and interpolation is realized in 65 nm CMOS. The proposed time-based offset calibration uses intentional timing skew for offset cancellation without adding extra load to comparators, thus avoiding the speed penalty. The time-based 4x interpolation reduces the number of comparators to 1/4 and provides calibration capability for 8-bit accuracy through SR latches and delay lines. At 2.8 GS/s, the prototype consumes 51 mW from a 1-V supply and achieves Nyquist SNDR of 43.3 dB, effective resolution bandwidth (ERBW) of 1.52 GHz, and Walden figure-of-merit (FoM) of 153 fJ/conv-step, reporting a higher Nyquist ENOB than state-of-the-art single-channel flash ADCs with comparable FoM.
基于时间偏移校准和插值的8位2.8 GS/s闪存ADC在65nm CMOS上实现。提出的基于时间的偏移校准使用故意的定时倾斜来抵消偏移,而不会给比较器增加额外的负载,从而避免了速度损失。基于时间的4x插值将比较器的数量减少到1/4,并通过SR锁存器和延迟线提供8位精度的校准能力。在2.8 GS/s的速度下,原型从1 v电源消耗51 mW,实现了43.3 dB的奈奎斯特SNDR, 1.52 GHz的有效分辨率带宽(ERBW)和153 fJ/ convo -step的Walden品质系数(FoM),报告了比具有相同FoM的最先进单通道闪存adc更高的奈奎斯特ENOB。
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引用次数: 9
Area Constrained Multi-Source Power Management for Thermoelectric Energy Harvesting 热电能量收集的面积约束多源电源管理
Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902907
Jacob Goeppert, Simon Braun, David Pellhammer, Mohammad Amayreh, J. Leicht, M. Keller, Y. Manoli
This paper presents a power management unit for a multi-source single-load system for thermoelectric energy harvesting. The system uses a conventional two-converter architecture and a time multiplexed hysteretic control scheme. The output voltage of four µTEGs with an open circuit voltage from 3 V to 5 V and an internal resistance of 2 kΩ to 8 kΩ are controlled into their respective maximum power point at a maximum measured tracking loss of 2.88 %. Tight system area design constraints require a high degree of integration and the use of a switched capacitor converter as well as an integrated low-dropout regulator. The system achieves a peak end-to-end efficiency of 37.7 % at the maximum input power of 4.44 mW. (Keywords: low power, power management, µTEG, micro energy harvesting)
介绍了一种用于多源单负荷热电能量采集系统的电源管理单元。该系统采用传统的双变换器结构和时间复用迟滞控制方案。四个开路电压为3v至5v,内阻为2 kΩ至8 kΩ的µteg的输出电压被控制在各自的最大功率点,最大测量跟踪损耗为2.88%。严格的系统面积设计约束要求高度集成化,并使用开关电容转换器以及集成的低差调节器。系统在最大输入功率为4.44 mW时,端到端效率达到37.7%的峰值。(关键词:低功耗,电源管理,µTEG,微能量收集)
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引用次数: 0
Power Analysis Resilient SRAM Design Implemented with a 1% Area Overhead Impedance Randomization Unit for Security Applications 功率分析弹性SRAM设计实现了1%的面积架空阻抗随机化单元,用于安全应用
Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902622
R. Giterman, Maoz Wicentowski, Oron Chertkow, I. Sever, Ishai Kehati, Y. Weizman, O. Keren, A. Fish
Power analysis attacks are an effective tool to extract sensitive information using side-channel analysis, forming a serious threat to IoT systems-on-a-chip (SoCs). Embedded memories implemented with conventional 6T SRAM macrocells often dominate the area and power of these SoCs. In this paper, for the first time, we use silicon measurements to prove that conventional SRAM arrays leak valuable information and that their data can be extracted using power analysis attacks. In order to provide a power analysis resilient embedded memory and adhere to the area constraints of modern SoCs, we implement a low-cost impedance randomization unit, which is integrated into the periphery of a conventional 6T SRAM macro. Preliminary silicon measurements of a 55 nm test-chip implementing the proposed memory array demonstrate a significant information leakage reduction at a low-cost 1% area overhead and no speed and power penalties compared to a conventional SRAM design.
功率分析攻击是利用侧信道分析提取敏感信息的有效工具,对物联网片上系统(soc)构成严重威胁。用传统的6T SRAM宏单元实现的嵌入式存储器通常在这些soc的面积和功率上占主导地位。在本文中,我们首次使用硅测量来证明传统的SRAM阵列泄漏有价值的信息,并且可以使用功率分析攻击提取其数据。为了提供功率分析弹性嵌入式存储器并遵守现代soc的面积限制,我们实现了一个低成本的阻抗随机化单元,该单元集成到传统6T SRAM宏的外围。采用该存储器阵列的55nm测试芯片的初步硅测量表明,与传统的SRAM设计相比,在低成本的1%面积开销下,显著减少了信息泄漏,并且没有速度和功耗损失。
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引用次数: 2
A 0.98-nW/kHz 33-kHz Fully Integrated Subthreshold-Region Operation RC Oscillator With Forward-Body-Biasing 一种0.98 nw /kHz 33-kHz正体偏置全集成亚阈值区域运算RC振荡器
Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902906
P. Fan, Anand Savanth, Benoît Labbé, Pranay Prabhat, James Myers
The lower bound on the power expended by an RC relaxation oscillator is decided by the RC network. This can be minimized by reducing the oscillation swing and increasing R. In the former technique, tighter comparator constraints limit power benefits while the latter technique increases resistor thermal noise bounding long-term jitter. To this end, this letter presents a fully integrated RC oscillator with core voltage aggressively scaled to subthreshold levels. A self-clocked switched-capacitor network is used to minimize voltage drop-out power loss. Full forward-body-biasing technique helps reduce device on-resistance. Additionally, temperature coefficient compensation for time constant is accomplished by poly resistors and a VTH-tracking reference scheme which avoids the use of diffusion resistors. This design is silicon-proven on 65-nm CMOS (0.0356-mm2 area). The implementation has a 33-kHz clock with 32.2 nW at 1.2 V. Line sensitivity is within +0.7/−0.6% per volt across 16 samples for 1 to 1.5 V. Temperature sensitivity was measured to be 56 ppm/°C from 0 °C to 85 °C and measured Allan deviation <100 ppm for averaging interval of τ = 400 s and <40 ppm for τ = 3000 s.
RC松弛振荡器的功耗下界由RC网络决定。这可以通过减小振荡摆幅和增加r来最小化。在前一种技术中,更严格的比较器约束限制了功率效益,而后一种技术增加了电阻热噪声边界长期抖动。为此,这封信提出了一个完全集成的RC振荡器,其核心电压积极缩放到亚阈值水平。采用自时钟开关电容网络,使电压降功率损失最小。完全前倾身体偏置技术有助于减少器件导通电阻。此外,温度系数补偿的时间常数是由多电阻和vth跟踪参考方案,避免使用扩散电阻。该设计在65纳米CMOS (0.0356 mm2面积)上进行了硅验证。该实现具有33khz时钟,在1.2 V时为32.2 nW。在1至1.5 V范围内,16个样品的线路灵敏度在+0.7/−0.6% /伏特内。从0°C到85°C,测量到的温度灵敏度为56 ppm/°C,在τ = 400 s的平均间隔内测量到的艾伦偏差<100 ppm, τ = 3000 s的平均间隔<40 ppm。
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引用次数: 4
Machine Learning Based Prior-Knowledge-Free Calibration for Split Pipelined-SAR ADCs with Open-Loop Amplifiers Achieving 93.7-dB SFDR 基于机器学习的开环分路管道sar adc无先验知识校准实现93.7 db SFDR
Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902873
Tianli Zhang, Yuefeng Cao, Shumin Zhang, Chixiao Chen, Fan Ye, Junyan Ren
The paper presents a machine-learning based calibration scheme for split pipelined-SAR ADCs with open-loop residual amplifiers. Different from conventional methods, the proposed scheme is prior-knowledge-free. The scheme adopts a two-layer neural network, and directly uses the bit-wise comparator results as inputs. The neural network compensates the distortion and can be compressed by 75% due to the network’s sparsity. A 14-bit 60-MSps split pipelined-SAR ADC with gain boosted dynamic amplifiers is fabricated in 28nm CMOS to validate the scheme. The measurement results show the ADC achieves an SFDR of 93.7 dB and an ENOB of 10.7b, consuming 2.79 mW. To the authors’ knowledge, it achieves the best SFDR among Nyquist ADCs with open-loop amplifiers.
提出了一种基于机器学习的开环残余放大器分路流水式sar adc标定方案。与传统方法不同,该方法不需要先验知识。该方案采用双层神经网络,直接使用逐位比较器结果作为输入。神经网络补偿了失真,由于网络的稀疏性,可以压缩75%。在28nm CMOS上制作了一个带增益增强动态放大器的14位60 msps分路流水线sar ADC来验证该方案。测量结果表明,该ADC的SFDR为93.7 dB, ENOB为10.7b,功耗为2.79 mW。据作者所知,它在带开环放大器的奈奎斯特adc中实现了最好的SFDR。
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引用次数: 8
A 5-Channel Unipolar Fetal-ECG Readout IC for Patch-Based Fetal Monitoring 一种用于贴片胎儿监护的5通道单极胎儿心电读出集成电路
Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902797
Roland Van Wegberg, J. Penders, C. Hoof, N. V. Helleputte, W. Sijbers, Shuang Song, Arjan Breeschoten, P. Vis, M. Konijnenburg, Hui Jiang, M. Rooijakkers, T. Berset
This letter presents a 5-channel unipolar fetal electrocardiogram readout IC for monitoring the health of a fetus during pregnancy. Each readout channel includes an instrumentation amplifier, a programable gain amplifier and a successive approximation register ADC. A unipolar, common half branch reuse topology is used to achieve low noise, low power, low crosstalk between the channels high input impedance and high CMRR at the same time. Each channel achieves an input referred noise of 0.47 µVrms in 0.5 to 150 Hz, while consuming a power of 43.2 µW. The 5-channel system provides a CMRR of 98 dB and an interchannel crosstalk rejection of 95 dB. The chip is implemented in a standard 55-nm CMOS process and occupies an area of 4.0 mm2. The whole chip, including five readout channels, leadoff detection, reference generation, autonomous data acquisition with on-chip sample storage and an interrupt-based serial peripheral host interface consumes a total power of 258 µW.
这封信提出了一个5通道单极胎儿心电图读出IC监测胎儿在怀孕期间的健康。每个读出通道包括一个仪表放大器、一个可编程增益放大器和一个逐次逼近寄存器ADC。采用单极、共半支路复用拓扑,实现低噪声、低功耗、通道间低串扰、高输入阻抗和高CMRR。在0.5 ~ 150hz范围内,每个通道的输入参考噪声为0.47µVrms,功耗为43.2µW。5通道系统的CMRR为98 dB,通道间串扰抑制为95 dB。该芯片采用标准的55纳米CMOS工艺,占地面积为4.0 mm2。整个芯片包括5个读出通道、引线检测、基准生成、带有片上样本存储的自主数据采集和基于中断的串行外设主机接口,总功耗为258µW。
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引用次数: 0
A 213.7-µW Gesture Sensing System-On-Chip With Self-Adaptive Motion Detection and Noise-Tolerant Outermost-Edge-Based Feature Extraction in 65 nm 基于自适应运动检测和抗噪声外缘特征提取的213.7µW手势传感片上系统
Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902612
Van Loi Le, Taegeun Yoo, Ju Eon Kim, K. Baek, T. T. Kim
This letter presents a low-power motion gesture recognition system-on-chip (SoC) for smart devices. The SoC incorporates a low-power image sensor and a memory-efficient outermost-edge-based gesture sensing DSP. The DSP utilizes a self-adaptive motion detector that automatically updates a motion-pixel threshold for accurately sensing hand movements. A convolution-based noise-tolerant feature extraction (FE) technique is also developed for preventing detection errors caused by random noises in the images from the low-power sensor. The FE architecture is highly accelerated utilizing parallelisms and pipelining for achieving low-latency real-time gesture recognition. Measurements from a test chip fabricated in 65-nm CMOS show that the SoC consumes 213.7 µW with only 3-µW dynamic power at 30 f/s. The SoC occupies only 0.54 mm2, making it well applicable for wearable devices and sensor nodes. The image sensor is fully operational down to 0.6 V while the DSP can be scaled down to 0.46 V. The average recognition accuracy of the system is 85% while the latency is 1.056 ms.
本文介绍了一种用于智能设备的低功耗动作手势识别片上系统(SoC)。该SoC集成了一个低功耗图像传感器和一个内存高效的基于外缘的手势传感DSP。DSP采用自适应运动检测器,自动更新运动像素阈值,以准确感知手部运动。为了防止低功耗传感器图像中随机噪声引起的检测误差,提出了一种基于卷积的耐噪声特征提取技术。FE架构是高度加速利用并行和流水线实现低延迟实时手势识别。65纳米CMOS测试芯片的测量结果表明,该SoC在30 f/s时功耗为213.7µW,动态功率仅为3µW。SoC占地面积仅为0.54 mm2,适用于可穿戴设备和传感器节点。图像传感器在0.6 V下完全工作,而DSP可以缩小到0.46 V。系统的平均识别准确率为85%,延迟为1.056 ms。
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引用次数: 7
CMOS interface with biological molecules and cells CMOS接口与生物分子和细胞
Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902832
Jeffrey Abbott, Tianyang Ye, Hongkun Park, D. Ham
CMOS technology and its Moore’s Law scaling is an enormously successful technology paradigm that has continued to transform our computation and communication abilities. Outside the applications in computation and communication, CMOS technology has been increasingly applied to the life sciences, with a wealth of silicon integrated circuits developed to interface with biological molecules and cells. Concretely, large-scale arrays of active electrodes are integrated using CMOS technology for highly parallel electronic detection of biomolecular/ionic charges and cellular potentials for DNA sequencing, molecular diagnostics, and electrophysiology. Parallelism enabled by CMOS scalability is well suited to process the big data in these biotechnological applications. Here we offer a brief review on these CMOS-bio interfaces, while the corresponding presentation will focus on a sub-topic of CMOS electrophysiology with mammalian neurons.
CMOS技术及其摩尔定律缩放是一种非常成功的技术范例,它继续改变着我们的计算和通信能力。除了在计算和通信方面的应用外,CMOS技术也越来越多地应用于生命科学,开发了大量的硅集成电路来与生物分子和细胞进行接口。具体来说,利用CMOS技术集成了大规模的活性电极阵列,用于生物分子/离子电荷和细胞电位的高度并行电子检测,用于DNA测序、分子诊断和电生理学。CMOS可扩展性带来的并行性非常适合处理这些生物技术应用中的大数据。在这里,我们将简要回顾这些CMOS-生物接口,而相应的演讲将集中在哺乳动物神经元CMOS电生理学的子主题上。
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引用次数: 2
An Integrated Programmable High-Voltage Bipolar Pulser With Embedded Transmit/Receive Switch for Miniature Ultrasound Probes 集成可编程高压双极脉冲发生器与嵌入式发射/接收开关的微型超声探头
Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902876
Mingliang Tan, E. Kang, Jae-Sung An, Z. Chang, P. Vince, N. Sénégond, M. Pertijs
This letter presents a compact programmable high-voltage (HV) pulser for ultrasound imaging, designed for driving capacitive micromachined ultrasonic transducers (CMUTs) in miniature ultrasound probes. To enable bipolar return-to-zero (RZ) pulsing and embedded transmit/receive switching, a compact back-to-back isolating HV switch is proposed that employs HV floating-gate drivers with only one HV MOS transistor each. The pulser can be digitally programmed to generate bipolar pulses with and without RZ, with a peak-to-peak swing up to 60 V, as well as negative and positive unipolar pulses. It can generate bursts of up to 63 pulses, with a maximum pulse frequency of 9 MHz for an 18-pF transducer capacitance. Realized in TSMC 0.18-µm HV BCD technology, the pulser occupies only 0.167 mm2. Electrical characterization results of the pulser, as well as acoustic results obtained in the combination with a 7.5-MHz CMUT transducer, are presented.
本文介绍了一种用于超声成像的紧凑型可编程高压(HV)脉冲发生器,设计用于驱动微型超声探头中的电容式微机械超声换能器(CMUTs)。为了实现双极归零(RZ)脉冲和嵌入式发射/接收开关,提出了一种紧凑的背对背隔离高压开关,该开关采用高压浮栅驱动器,每个驱动器只有一个高压MOS晶体管。脉冲发生器可以通过数字编程产生带或不带RZ的双极脉冲,峰对峰摆幅高达60 V,以及负和正单极脉冲。它可以产生多达63个脉冲的脉冲,对于18pf换能器电容,最大脉冲频率为9 MHz。采用台积电0.18µm HV BCD技术实现,脉冲发生器的占地面积仅为0.167 mm2。给出了脉冲发生器的电特性结果,以及与7.5 mhz CMUT换能器结合获得的声学结果。
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引用次数: 0
A 26-Gb/s 3-D-Integrated Silicon Photonic Receiver in BiCMOS-55 nm and PIC25G With – 15.2-dBm OMA Sensitivity 具有- 15.2 dbm OMA灵敏度的bicmos - 55nm和PIC25G的26gb /s三维集成硅光子接收器
Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902549
Farhad Bozorgi, M. Bruccoleri, M. Repossi, E. Temporiti, A. Mazzanti, F. Svelto
This letter presents a 3-D-integrated 26 Gb/s opto-electrical receiver front-end. The electronic integrated circuit (EIC) is fabricated in a BiCMOS-55-nm technology, flipped and placed on top of the photonic integrated circuits (PICs) die through copper pillars. In the receiver chain, a fully differential shunt-feedback TI amplifier (FD-SF TIA) is followed by a limiting amplifiers (LAs) with embedded equalization, output driver and an automatic offset cancelation loop. The whole receiver provides a transimpedance (TI) gain of 76 dBñ with 30-GHz bandwidth. By exploiting the FD-SF TIA with low parasitic capacitance of the Germanium dual heterojunction photo diode (Ge-PD) in the photonic die, the receiver achieves sensitivity of −15.2 dBm optical modulation amplitude (OMA) at Ge-PD and −10-dBm OMA at the single-mode fiber (SMF) optical output with bit error rate of 10−12 and PRBS 15. The sensitivity is aligned with state-of-the-art receivers employing discrete photonics and, to author’s best knowledge, it is the lowest reported among published 25 Gb/s receivers exploiting silicon photonics.
这封信介绍了一个3d集成的26gb /s光电接收器前端。电子集成电路(EIC)采用bicmos -55纳米技术制造,通过铜柱翻转并放置在光子集成电路(PICs)芯片的顶部。在接收器链中,一个全差分并联反馈TI放大器(FD-SF TIA)之后是一个具有嵌入式均衡、输出驱动器和自动偏移抵消回路的限制放大器(LAs)。整个接收机在30 ghz带宽下提供76 dBñ的透阻(TI)增益。通过利用光子芯片中锗双异质结光电二极管(Ge-PD)低寄生电容的FD-SF TIA,接收器在Ge-PD处实现了−15.2 dBm的光调制幅度(OMA),在单模光纤(SMF)光输出处实现了−10 dBm的光调制幅度(OMA),误码率为10−12,PRBS为15。灵敏度与采用离散光子学的最先进的接收器一致,据作者所知,它是已发表的利用硅光子学的25 Gb/s接收器中报道的最低的。
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引用次数: 0
期刊
ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)
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