0.6 /spl mu/m Pitlch Highly Reliable Multilevel Interconnection Using Hydrogen Silicate Based Inorganic SOG For Sub-quarter Micron CMOS Technology

Abstract

A 0.6 p pitch highly reliable multilevel interconnection technology using low-k Hydrogen Silicate Based Inorganic Spinon Glass (HSI-!SOG) is demonstrated for 0.15 p CMOS devices. A stable HSI-SOG interlayer dielectric (ILD) with low leakage current is realized in the metallization process with above 400 “c. The reliability of wiring and MOSFET is superior to that of the conventional high-density plasma CVD Si02 (HDP S i 0 4 ILD. A new via formation process using an NH3 plasma treatment achieves low via resistance of 4 Cl at 0.28 pm in diameter. In addition, the device performance is also improved by the 25 % reduction in wiring capacitance. Introduction Low-k ILD is indispensable to high performance W I such as high-end process,ors and “System on a chip”, because it can reduce not only the wiring delay but also power dissipation [l]. Though organic polymers [2] have very low dielectric constants (~=2.0-2.5), they have some problems such as the thermal instability or the difficulty of via formation. HSI-SOG is very attractive because of its low dielectric constant and high thermal stability which t a maintain compatibility with conventional metallization process. There are several reports that have investigated the performance of inorganic SOG in 0.35 pm technology[3, 41. However, the integration issues such as via resistance, wiring reliability and transistor reliability have not been evaluated falr sub-quarter-micron CMOS. In this paper, integration of HSI-SOG into total CMOS process in 0.15 p generation is examined. An NH3 plasma treatment technology is proposed to avoid poisoned vias. The reliability of wining and hot-carrier immunity of MOSFET, as well as the device performance, are also evaluated. Experimental A 0.6 pm pitclh multilevel metallization using HSI-SOG was constructed on 0.15 pm CMOS. In ILD process, plasma-TEOS Si02 was deposited on HSI-SOG, followed by planarization using CMP. The via formation process is shown in Fig. 1. After resist stripping, ithe NH3 plasma treatment was performed to passivate the sidewalls of the vias. The maximum process temperature was 420 “c at the W CVD step. Evaluated feature sizes are from 0.3/0.3 to 0.5/0.5 pm for wiring line/space and from 0.28 to 0.5 pm for vias. Results and Discussion An SEM cross-sectional view of the multilevel metallization is shown in Fig. 2. A good gap-filling capability is observed in spaces down to 0.3 pm. No crack is observed after the metallization process. Measured adjacent wiring capacitance is shown in Fig. :3. Wiring capacitance is reduced by 25 % compared with the HDP Si02. The estimated dielectric constant of HSI-SOG is 3.0. Simulated Tpd for 0.15 pm CMOS 2NAND with wiring is shown in Fig. 4. The HSI-SOG ILD achieves 18 % reduction in Tpd for the typical global wiring length of 10 mm, compared with the HDP-Si02 LLD. The leakage current between the adjacent metals is shown in Fig. 5. The leakage current is stable and comparable to HDPSi02 ILD even at 0.3 pm wiring space. Via resistance dependence on via size is shown in Fig. 6. A very low resistance of 4 fl for 0.28 pm via is obtained by using the NH3 plasma treatment. It could be considered that the moisture absorbed in HSI-SOG during the wet resist stripping step can be capped by nitrided sidewalls formed at the subsequent NH3 plasma treatment step. Stress migration test results for wiring are shown in Fig. 7. There is no difference in behavior between the two ILD structures. This result indicates that the internal stress in HSISOG could also be low. The hot-canier lifetime of 0.15 pm nMOSFET is shown in Fig. 8. The lifetime of nMOSFET with HSI-SOG is about one order of magnitude longer than that with HDP SiOz. This could be caused by the fact that the amount of Si-OH in HSI-SOG is smaller than that in HDP Si02 as shown in IT-IR spectrum (Fig. Conclusions A 0.6-pm pitch multilevel interconnection using HSI-SOG has been demonstrated for 0.15 pm CMOS devices. A HSI-SOG with high reliability and thermal stability has been achieved. In addition to the excellent reliability, the device performance has been improved by the reduction of the wiring capacitance. The HSI-SOG is the most promising ILD for sub-quarter-micron CMOS devices. Acknowledgments The authors would like to thank H. Ishikawa, K. Koyanagi, Y. Tsuchiya, K. Tokashiki, and H. Iwasaki for their technical suggestions. References [l] K. Rahmas 0. S. Nakagawa, S-Y. Oh, J. Moll, and W. T. Lynch, IEDM Tech. Digest (1995) p.245. [2] K. S. Y. Lau et al., Proceedings of VMIC (1996) p.92. [3] B. T. Ahlbum, et al., Conference F’roeedmgs ULSI XI M R S (1996) p.67. [4] T. Zoes, B. A h l b q K. Em, and M.Marsden, Conference Proceedings ULSI X I M R S (1996) p.121. [5] M. Takagi, I. Yoshii, and K. Hashimoto, IEDM Tech. Digest (1992) p.703. 9) ~51. 79 4-93081 3-75-1 I97 1997 Symposium on VLSl Technology Digest of Technical Papers