A study of 0.10 pm gate sheet resistance and the most relevant device characteristics comparing Ti salicide with preamorphization, Ti salicide with Molybdenum doping, and CO salicide in a fully integrated 0.18~ 1.5V CMOS technology is presented for the first time. We report the first one-step RTP Ti salicide process with MO achieving low (mean=7, max=8.1 R/sq) sheet resistance at 0.10 pn gate lengths, which results in a 34% increase in n- and PMOS DRIVE by eliminating the silicide anneal step. While low 0. lop gate sheet resistances are achieved with all these processes (a) TiSiz with MO doping of gate only and (b) COS& with high temperature RTP appear as the best suited salicides for scaled technologies with low DIODE and high DRIVE In contrast (a) DIODE increases when source and drains are also doped with MO and (b) R~D increases with As or Ge preamorphization notably as junctions are scaled down.
{"title":"Salicides for 0.10 /spl mu/m gate lengths: a comparative study of one-step RTP Ti with Mo doping, Ti with pre-amorphization and Co process","authors":"Kittl, Qi-Zhong Hong, Chih-Ping Chao, Ih-Chin Chen, Ning Yu, O'Brien, Hanratty","doi":"10.1109/VLSIT.1997.623716","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623716","url":null,"abstract":"A study of 0.10 pm gate sheet resistance and the most relevant device characteristics comparing Ti salicide with preamorphization, Ti salicide with Molybdenum doping, and CO salicide in a fully integrated 0.18~ 1.5V CMOS technology is presented for the first time. We report the first one-step RTP Ti salicide process with MO achieving low (mean=7, max=8.1 R/sq) sheet resistance at 0.10 pn gate lengths, which results in a 34% increase in n- and PMOS DRIVE by eliminating the silicide anneal step. While low 0. lop gate sheet resistances are achieved with all these processes (a) TiSiz with MO doping of gate only and (b) COS& with high temperature RTP appear as the best suited salicides for scaled technologies with low DIODE and high DRIVE In contrast (a) DIODE increases when source and drains are also doped with MO and (b) R~D increases with As or Ge preamorphization notably as junctions are scaled down.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"72 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124863250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623700
Schwalke, Kerber, Koller, Ludwig, Seidl
In this work we present the advanced gate-stack architecture EXTIGATE (Extended Trench Isolation GAte TEchnology) which solves major problems associated with n+/p+ dual workfunction gate technology and shallow-trench-isolation (STI). These achievements are realized without an increase in process complexity. Furthermore, the process window is enlarged leading to a robust low-voltage dual-workfunction STI-CMOS process.
{"title":"Advanced Gate-stack Architecture For Low-voltage Dual-workfunction CMOS Technologies With Shallow Trench Isolation","authors":"Schwalke, Kerber, Koller, Ludwig, Seidl","doi":"10.1109/VLSIT.1997.623700","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623700","url":null,"abstract":"In this work we present the advanced gate-stack architecture EXTIGATE (Extended Trench Isolation GAte TEchnology) which solves major problems associated with n+/p+ dual workfunction gate technology and shallow-trench-isolation (STI). These achievements are realized without an increase in process complexity. Furthermore, the process window is enlarged leading to a robust low-voltage dual-workfunction STI-CMOS process.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"255 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122361464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623667
Komiya
Development of the 300¿ technology is approaching the exciting part of the program. The transition in the wafer diameter fiom 200¿ to 300¿ is expected to result in the chip cost reduction by the range of 1.520% and to decrease the investment in the production line down to about 65%. The technological key issues would be the crystal growth and the heat treatment. World-wide cooperative efforts are being made for the evaluation of the equipment and materials and for the standardiition.
{"title":"The 300mm Technology Current Status And Future Prospect","authors":"Komiya","doi":"10.1109/VLSIT.1997.623667","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623667","url":null,"abstract":"Development of the 300¿ technology is approaching the exciting part of the program. The transition in the wafer diameter fiom 200¿ to 300¿ is expected to result in the chip cost reduction by the range of 1.520% and to decrease the investment in the production line down to about 65%. The technological key issues would be the crystal growth and the heat treatment. World-wide cooperative efforts are being made for the evaluation of the equipment and materials and for the standardiition.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129323384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A fully planarized stacked capacitor cell for lGiga bit DRAM and beyond having three significant features has been developed. First, all the lithograpluc processes were performed on the planarized surface to achieve enough margin. Second, the patterns in critical layers were arranged to be suitable for alternating Phase Shift Mask(PSM). Third, deep contact hole resulting from introducing global planarization was adopted in a reasonable size. The cell area of 0.26um2 (0.36 x 0.72~) can be fabricated with a KrF excimer stepper using five alternating PSMs and two half tone PSMs. 1 nt rod ucti o n DRAM process development has been hghly depend on the development of lithographic technologies. But optical lithography is now facing severe problems such as wavelength limitation and insufficient overlay accuracy. Moreover, the steps between cell array and peripheral circuit area become serious problem more and more to perform DRAM process because the cell capacitance has to be maintained in each generation. The steps require a large depth of focus (DOF), restrict a design rule scaling, and also make etching of first metal layer very difficult. As a result, the chip size will be larger. To overcome the above problems, we have selected photo-lithography-fiiendly technology which means straight line and space pattern, fully planarized surface, and adopting alternating PSM. We also used a self aligned contact (SAC) technology to achieve 8F2 cell size. The fully planarized cells were reported, but they used larger cell size and relaxed design A global planarization is very attractive, but has disadvantage, which is deep and hence high aspect ratio (HAR) contact hole. We have fabricated and confumed contact resistance and junction leakage with HAR contact hole necessitated by global planarization after capacitor formation in 0.1 Sum rule. This paper describes a novel DRAM cell concept and fabrication process in 0.18~ rule with HAR contact for the fxst time.
开发了一种用于lGiga位及以上DRAM的完全平面化堆叠电容器电池，具有三个重要特征。首先，所有的光刻过程都在平面表面进行，以获得足够的余量。其次，对关键层的图形进行了适合于交变相移掩模(PSM)的排列。三是采用合理尺寸的引入全局平面化后形成的深接触孔。使用5个交变psm和2个半音psm，可以用KrF准分子步进制得0.26um2 (0.36 x 0.72~)的细胞面积。DRAM工艺的发展在很大程度上依赖于光刻技术的发展。但光刻技术目前面临着波长限制和覆盖精度不足等严重问题。此外，由于每一代都要保持单元电容，因此单元阵列与外围电路区域之间的间距问题越来越严重。这些步骤需要很大的焦深(DOF)，限制了设计规则的缩放，也使得第一金属层的蚀刻非常困难。因此，芯片尺寸将更大。为了克服上述问题，我们选择了光刻友好技术，即直线和空间图案，完全平面化的表面，采用交替的PSM。我们还使用了自对准接触(SAC)技术来实现8F2单元尺寸。完全平面化的细胞有报道，但它们使用了更大的细胞尺寸和宽松的设计。整体平面化是非常有吸引力的，但缺点是接触孔深，因此高纵横比(HAR)。在0.1 Sum规则下，我们制作并混淆了电容形成后全局平面化所需要的HAR接触孔的接触电阻和结漏。本文首次提出了一种新的具有HAR接触的0.18~规则的DRAM单元概念和制造工艺。
{"title":"Fully Planarized Stacked Capacitor Cell With Deep And High Aspect Ratio Contact Hole For Gigs-bit DRAM","authors":"Itabashi, Tsuboi, Nakamura, Hashimoto, Futoh, Fukuda, Hanyu, Asai, Kawamura, Yao, Takagi, Ohta, Karasawa, Iio, Inoue, Nomura, Satoh, Higashimoto, Matsumiya, Miyabo, Ikeda, Yamazaki, Miyajima, Watanabe, Taguchi","doi":"10.1109/VLSIT.1997.623675","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623675","url":null,"abstract":"A fully planarized stacked capacitor cell for lGiga bit DRAM and beyond having three significant features has been developed. First, all the lithograpluc processes were performed on the planarized surface to achieve enough margin. Second, the patterns in critical layers were arranged to be suitable for alternating Phase Shift Mask(PSM). Third, deep contact hole resulting from introducing global planarization was adopted in a reasonable size. The cell area of 0.26um2 (0.36 x 0.72~) can be fabricated with a KrF excimer stepper using five alternating PSMs and two half tone PSMs. 1 nt rod ucti o n DRAM process development has been hghly depend on the development of lithographic technologies. But optical lithography is now facing severe problems such as wavelength limitation and insufficient overlay accuracy. Moreover, the steps between cell array and peripheral circuit area become serious problem more and more to perform DRAM process because the cell capacitance has to be maintained in each generation. The steps require a large depth of focus (DOF), restrict a design rule scaling, and also make etching of first metal layer very difficult. As a result, the chip size will be larger. To overcome the above problems, we have selected photo-lithography-fiiendly technology which means straight line and space pattern, fully planarized surface, and adopting alternating PSM. We also used a self aligned contact (SAC) technology to achieve 8F2 cell size. The fully planarized cells were reported, but they used larger cell size and relaxed design A global planarization is very attractive, but has disadvantage, which is deep and hence high aspect ratio (HAR) contact hole. We have fabricated and confumed contact resistance and junction leakage with HAR contact hole necessitated by global planarization after capacitor formation in 0.1 Sum rule. This paper describes a novel DRAM cell concept and fabrication process in 0.18~ rule with HAR contact for the fxst time.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"284 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114373997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623709
Shishiguchi, Mineji, Hayashi, Saito
This paper proposes a novel 50nm-depth shallow junction formation for realizing low SD-extension resistance in deep sub-quarter micron PMOS-FETs. In this technology, the extension is fabricated by Ge'(5keV) pre-amorphizised lowenergy B'( 1 keV) implantation, followed by optimized RTA condition (1 100°C for 50msec with ramping-rate 400"C/sec). It has become apparent that this optimized condition yields the lower resistance-limit(300~/sq) for 50nm-depth junction, when using ion implantation process. S/D series resistance for the O.15ym-PMOS(W= IOym) fabricated by this technology is reduced to 140R. This result shows that high-performance deep sub-quarter micron CMOS-FETs are realized by the optimization of ion implantation and/or RTA process.
{"title":"Boron Implanted Shallow Junction Formation By High-temperature/ Short-time/high-ramping-rate(400/spl deg/C/sec) RTA","authors":"Shishiguchi, Mineji, Hayashi, Saito","doi":"10.1109/VLSIT.1997.623709","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623709","url":null,"abstract":"This paper proposes a novel 50nm-depth shallow junction formation for realizing low SD-extension resistance in deep sub-quarter micron PMOS-FETs. In this technology, the extension is fabricated by Ge'(5keV) pre-amorphizised lowenergy B'( 1 keV) implantation, followed by optimized RTA condition (1 100°C for 50msec with ramping-rate 400\"C/sec). It has become apparent that this optimized condition yields the lower resistance-limit(300~/sq) for 50nm-depth junction, when using ion implantation process. S/D series resistance for the O.15ym-PMOS(W= IOym) fabricated by this technology is reduced to 140R. This result shows that high-performance deep sub-quarter micron CMOS-FETs are realized by the optimization of ion implantation and/or RTA process.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134341331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The progressive scaling of Dd cells towards 8F2 for the 1G generation and beyond requires to design, both channel length and width of the array device in minimum dimensions. Historically the DRAM array device was kept conservatively large to ensure a wide process window for the stringent off current requirement as well as a relaxed doping level to minimize junction fields and leakage [l]. In thls paper , data is presented showing that narrow width effects become dominant in the array transistor design and control of the comer device associated with the shallow trench isolation becomes crucial. A novel Raised Shallow Trench Isolation (RSTI) is proposed as a way of structurally reducing the influences of STI related comer conduction on threshold voltage. This scheme was introduced earlier for the purpose of reducing the size of NAND EEPROM [2] and SRAM cells [3] as well as for a CMOS process [4] . We show its integration into a DRAM cell for the first time and present data showing the extremely tight control of array threshold voltage achievable with this process.
{"title":"A Novel 1b Trench DRAM Cell With Raised Shallow Trench Isolation (RSTI)","authors":"Alsmeier, Kelleher, Beintner, Haensch, Mandelman, Hoh, Ninomiya, Srinivasan, Bronner","doi":"10.1109/VLSIT.1997.623674","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623674","url":null,"abstract":"The progressive scaling of Dd cells towards 8F2 for the 1G generation and beyond requires to design, both channel length and width of the array device in minimum dimensions. Historically the DRAM array device was kept conservatively large to ensure a wide process window for the stringent off current requirement as well as a relaxed doping level to minimize junction fields and leakage [l]. In thls paper , data is presented showing that narrow width effects become dominant in the array transistor design and control of the comer device associated with the shallow trench isolation becomes crucial. A novel Raised Shallow Trench Isolation (RSTI) is proposed as a way of structurally reducing the influences of STI related comer conduction on threshold voltage. This scheme was introduced earlier for the purpose of reducing the size of NAND EEPROM [2] and SRAM cells [3] as well as for a CMOS process [4] . We show its integration into a DRAM cell for the first time and present data showing the extremely tight control of array threshold voltage achievable with this process.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131406160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623685
Neugroschel, Chih-Tang Sah
A new physical model on electrical degradation of the metaYpolysilicodsilicon contact at high current densities is presented and verified by experiments. Results from submicron n+poly/n+emitter/p-base/n+collector bipolar transistors indicate that the observed contact instabilities are reaction rate limited by transient dehydrogenation and hydrogenation at the n+poly/n+emitter interface and steady-state dehydrogenation at the metal/n+poly interface. Introduction Scaling down transistors in present and future integrated circuits increases the current densities which pass through the interconnect/silicon contacts. Thus, the long-term stability of the contacts in BJTs and MOSTs can be a potential reliability problem. Instabilities of the emitter contact resistance RE and current gain pF were observed in submicron B JT’s with metal/n+poly-silicon/n+siliconemitter (metaVn+poly/n+emitter) structure when stressed at h i g h f o r w a r d e m i t t e r c u r r e n t d e n s i t y JE-s t ress > -1.0mA/pm2 [ 1-31. Detail experiments on contact instability were reported recently [3] showing increasing and decreasing pF with stress time and two rate constants both with A,J, + A,Ji dependency. These dependencies were attributed to the hydrogenation and dehydrogenation reactions at the metal/poly-Si and poly-Si/c-Si interfaces. However, a viable physics-based theory to explain and model the instability dependencies on current density was not given in [3] which is presented here. Model and Experiments Figure 1 (a) shows the hydrogenation-dehydrogenation pathways in the metal/n+poly/n+emitter structure of the BJT used in the experiment and the physical model development [4]. Electrons (filled circles) flow into the contact which is forward-biased to V, = 1V to 2V. Holes (open circles) are injected from the p-base into the n+poly and n+emitter layers. The limiting transient reaction is the hydrogenation-dehydrogenation at the n+poly/n+emitter interface which decrease-increase respectively the density of the interfacial silicon and oxygen dangling bonds, Si. and SiO., where electrons and holes recombine to give I, and control pF. The rate equation for the density of one interfacial trap species, nIT(t), its solution for a steady-state hydrogen concentration, and the rate constants are given below which account for all the experimental variations observed in [31. Metal n+polySi ncEmitter p-Base Fig.1 Creation and destruction of interface traps i n the metal/n+poly/n+emitter/p-base contact layers at high forward current densities. (a) Cross-section with kinetics pathways. (b) Transition energy band diagram. NITT in (3) i s t h e t o t a l i n t e r f a c i a l t r a p d e n s i t y , hydrogenated plus not-hydrogenated. The initial and final value, nIT(t=O)=NIT0 and nIT(t=m)ENITm determines whether pF decreases (NIT0 < NIT,) or increases (NIT? > NIT,) with s t r e s s t i m e , wh ich i s c o n s i s t e n t wi th 41 4-93081 3-75-1 197 1997 Symposium on VLSl Technolog
提出了一种新的高电流密度下超多晶硅接触电降解的物理模型，并通过实验进行了验证。亚微米n+poly/n+发射极/p-base/n+集电极双极晶体管的实验结果表明，接触不稳定性受n+poly/n+发射极界面的瞬态脱氢和加氢以及金属/n+poly界面的稳态脱氢的限制。在当前和未来的集成电路中，缩小晶体管会增加通过互连/硅触点的电流密度。因此，bjt和most中触点的长期稳定性可能是一个潜在的可靠性问题。在金属/n+多晶硅/n+硅发射极(metaVn+poly/n+发射极)结构的亚微米B - JT中，当应力> -1.0mA/pm2时，观察到发射极接触电阻RE和电流增益pF的不稳定性[1-31]。最近报道的接触不稳定性的详细实验[3]表明，pF随应力时间的增加和减少，两个速率常数都与A,J， + A,Ji相关。这些依赖关系归因于金属/多晶硅和多晶硅/c-Si界面上的加氢和脱氢反应。然而，在[3]中并没有给出一个可行的基于物理的理论来解释和模拟电流密度对不稳定性的依赖关系。图1 (a)显示了实验中使用的BJT金属/n+聚/n+发射极结构的加氢-脱氢途径和物理模型的建立[4]。电子(填充的圆圈)流入正向偏置到V的触点，= 1V到2V。孔(开圆)从p基注入到n+聚层和n+发射极层。极限瞬态反应是在n+poly/n+发射极界面处的加氢-脱氢反应，分别使界面硅和氧悬空键Si的密度降低-增加。和SiO。，其中电子和空穴重新组合产生I，并控制pF。下面给出了一种界面陷阱物种密度的速率方程，nIT(t)，稳态氢浓度的解，以及速率常数，它们解释了[31]中观察到的所有实验变化。图1高正向电流密度下金属/n+poly/n+emitter/ p-Base接触层中界面陷阱i的产生和破坏。(a)带有动力学路径的截面。(b)过渡能带图。(3)里的NITT是氢化的和非氢化的，它是氢化的和非氢化的。初始值和最终值nIT(t= 0)=NIT0和nIT(t=m)ENITm决定pF是减小(NIT0 < nIT，)还是增大(nIT ?> NIT)和s t r e s s t i m e, wh我我s c o n s s t e n t wi th 41 4 - 93081 3-75-1 197 1997研讨会VLSl技术消化技术论文其实达[3]t l o w和本坏蛋任t窝点我分别。初始(预应力)值由制造工艺决定，最终状态稳定值NIT由开启JE后立即达到的稳态可移动(脱氢)氢浓度决定，其速度比NIT (t)的时间依赖性快得多，因为氢气的来源在金属/n+多界面处，这里的捕氢位点浓度很高，而脱氢和可移动氢浓度相对较低。由于氢气在n+poly/n+发射器界面上的扩散速率比nIT(t)的时间依赖性大。图1 (a)所示的金属/n+多界面上的两种反应机制给出了与dJ和JE成正比的稳态氢浓度。由式(5)和式(6)给出的N2P速率(t)有线性的氢捕获部分，氢发射部分由氢键断裂决定，其速率为两个热电子和一个空穴的俄盖复合产生的热电子的浓度，其速率与N2P成正比。在低JE时，N +poly/ N +发射极区的电子浓度N为:N +的电子浓度N为:N +的电子浓度N为:N +的电子浓度N为:N +的电子浓度N, N +的电子浓度N为:N +的电子浓度N, N +的电子浓度N为:N +的电子浓度N, N +的电子浓度N为:N +的电子浓度P为:当P -碱达到高注入水平时，电子浓度P与JE成正比，即eH 0~ Ho与h′的电子浓度P如(5)所示。当高乙脑时，N和P都与乙脑渐近成正比，使得eH = J i如(6)所示。这些电流密度依赖关系在图2中增加或减少of的应力时间依赖关系中观察到-AIB/IBo。动力学很好地符合(2)给出的两种界面陷阱的时间常数和在[3]中观察到的T~的指数依赖性，归因于占主导地位的n+poly/n+Si Si。
{"title":"Physical Model For Contact Degradation At High Current Densities","authors":"Neugroschel, Chih-Tang Sah","doi":"10.1109/VLSIT.1997.623685","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623685","url":null,"abstract":"A new physical model on electrical degradation of the metaYpolysilicodsilicon contact at high current densities is presented and verified by experiments. Results from submicron n+poly/n+emitter/p-base/n+collector bipolar transistors indicate that the observed contact instabilities are reaction rate limited by transient dehydrogenation and hydrogenation at the n+poly/n+emitter interface and steady-state dehydrogenation at the metal/n+poly interface. Introduction Scaling down transistors in present and future integrated circuits increases the current densities which pass through the interconnect/silicon contacts. Thus, the long-term stability of the contacts in BJTs and MOSTs can be a potential reliability problem. Instabilities of the emitter contact resistance RE and current gain pF were observed in submicron B JT’s with metal/n+poly-silicon/n+siliconemitter (metaVn+poly/n+emitter) structure when stressed at h i g h f o r w a r d e m i t t e r c u r r e n t d e n s i t y JE-s t ress > -1.0mA/pm2 [ 1-31. Detail experiments on contact instability were reported recently [3] showing increasing and decreasing pF with stress time and two rate constants both with A,J, + A,Ji dependency. These dependencies were attributed to the hydrogenation and dehydrogenation reactions at the metal/poly-Si and poly-Si/c-Si interfaces. However, a viable physics-based theory to explain and model the instability dependencies on current density was not given in [3] which is presented here. Model and Experiments Figure 1 (a) shows the hydrogenation-dehydrogenation pathways in the metal/n+poly/n+emitter structure of the BJT used in the experiment and the physical model development [4]. Electrons (filled circles) flow into the contact which is forward-biased to V, = 1V to 2V. Holes (open circles) are injected from the p-base into the n+poly and n+emitter layers. The limiting transient reaction is the hydrogenation-dehydrogenation at the n+poly/n+emitter interface which decrease-increase respectively the density of the interfacial silicon and oxygen dangling bonds, Si. and SiO., where electrons and holes recombine to give I, and control pF. The rate equation for the density of one interfacial trap species, nIT(t), its solution for a steady-state hydrogen concentration, and the rate constants are given below which account for all the experimental variations observed in [31. Metal n+polySi ncEmitter p-Base Fig.1 Creation and destruction of interface traps i n the metal/n+poly/n+emitter/p-base contact layers at high forward current densities. (a) Cross-section with kinetics pathways. (b) Transition energy band diagram. NITT in (3) i s t h e t o t a l i n t e r f a c i a l t r a p d e n s i t y , hydrogenated plus not-hydrogenated. The initial and final value, nIT(t=O)=NIT0 and nIT(t=m)ENITm determines whether pF decreases (NIT0 < NIT,) or increases (NIT? > NIT,) with s t r e s s t i m e , wh ich i s c o n s i s t e n t wi th 41 4-93081 3-75-1 197 1997 Symposium on VLSl Technolog","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128521938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623706
Shih, Chang, Havemann, Levine
{"title":"Implication And Solutions For Joule Heating In High Performance Interconnects Incorporating Low-k Dielectrics","authors":"Shih, Chang, Havemann, Levine","doi":"10.1109/VLSIT.1997.623706","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623706","url":null,"abstract":"","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"220 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129674598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623683
Vos, Rotondaro, Mertens, Meuris, Heyns
Corrosion of metal lines during the post-stripping rinse is a severe problem in multi-level metallization processes. In this paper it is demonstrated that the addition of small amounts of the inorganic acid HNO3 to the ultrapure water used for rinsing can effectively be used to suppress this corrosion without the need of an additional IPA- step.
{"title":"A Novel Environmentally-friendly Corrosion-free Post-stripping Rinsing Procedure After Solvent Strip","authors":"Vos, Rotondaro, Mertens, Meuris, Heyns","doi":"10.1109/VLSIT.1997.623683","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623683","url":null,"abstract":"Corrosion of metal lines during the post-stripping rinse is a severe problem in multi-level metallization processes. In this paper it is demonstrated that the addition of small amounts of the inorganic acid HNO3 to the ultrapure water used for rinsing can effectively be used to suppress this corrosion without the need of an additional IPA- step.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127110085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623697
Choi, Kim, Shin, Mang, Ahn
Introduction With this programming method, a program speed of 300 ,us, which is equivalent to that of the single bit NAND cell, is The Multi-Level Cell (MLC) technology is essential in achieved. The parallel programming with booster-lines significantly reducing the bit cost of flash memories [I]. results in a significant improvement over the conventional The MLC, however, has drawbacks such as high MLC which requires a high programming voltage of over 20 programming voltage, longer programming time and V and prolonged programming time [ 11. increased disturbances. We demonstrated in the Dast that the booster plate Multi-Level Cell Characteristics NAND flash technology enhances the program speed and eliminates the program disturbance [2]. In this paper, we report a new fast parallel programming method for MLC NAND. With the addition of booster-lines to the cell strings, the program speed of each NAND string can be controlled by the booster-line bias. This method in essence is to obtain different cell threshold voltages ( v t h ) at a given programming time by controlling the program voltage of individual memory cells. Thus the four-level MLC with programming speed and reliability comparable to those of the single bit NAND cell is achieved. Fig. 4 shows that the measured Vth’s of the four-level cell array (4k bits) have tight distributions of less than 0.5 V. The erase characteristics are almost independent of the Vth levels as shown in Fig. 5 . Due to high programming voltage and long programming time, unselected cells in conventional MLC’s are exposed to increased disturbances. The adoption of booster-lines, however, results in a wide Vpws zone without Program voltage disturbance (Vpgm stress) and Vpass stress at pass voltage less than 7 V, as shown in Fig. 6. The complete disappearence of the Vpgm stress is caused by the enhanced self-boosting action in program inhibited cells by boosterlines [2]. It is important to have enough sensing margin in MLC because of the reduced Vth windows. The “ON” cell string current is the smallest when the difference between the cell Cell Structure and Operation
{"title":"Fast Parallel Programming Of Multi-level NAND Flash Memory Cells Using The Booster-line Technology","authors":"Choi, Kim, Shin, Mang, Ahn","doi":"10.1109/VLSIT.1997.623697","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623697","url":null,"abstract":"Introduction With this programming method, a program speed of 300 ,us, which is equivalent to that of the single bit NAND cell, is The Multi-Level Cell (MLC) technology is essential in achieved. The parallel programming with booster-lines significantly reducing the bit cost of flash memories [I]. results in a significant improvement over the conventional The MLC, however, has drawbacks such as high MLC which requires a high programming voltage of over 20 programming voltage, longer programming time and V and prolonged programming time [ 11. increased disturbances. We demonstrated in the Dast that the booster plate Multi-Level Cell Characteristics NAND flash technology enhances the program speed and eliminates the program disturbance [2]. In this paper, we report a new fast parallel programming method for MLC NAND. With the addition of booster-lines to the cell strings, the program speed of each NAND string can be controlled by the booster-line bias. This method in essence is to obtain different cell threshold voltages ( v t h ) at a given programming time by controlling the program voltage of individual memory cells. Thus the four-level MLC with programming speed and reliability comparable to those of the single bit NAND cell is achieved. Fig. 4 shows that the measured Vth’s of the four-level cell array (4k bits) have tight distributions of less than 0.5 V. The erase characteristics are almost independent of the Vth levels as shown in Fig. 5 . Due to high programming voltage and long programming time, unselected cells in conventional MLC’s are exposed to increased disturbances. The adoption of booster-lines, however, results in a wide Vpws zone without Program voltage disturbance (Vpgm stress) and Vpass stress at pass voltage less than 7 V, as shown in Fig. 6. The complete disappearence of the Vpgm stress is caused by the enhanced self-boosting action in program inhibited cells by boosterlines [2]. It is important to have enough sensing margin in MLC because of the reduced Vth windows. The “ON” cell string current is the smallest when the difference between the cell Cell Structure and Operation","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130006227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：