{"title":"A new characterization of sub-/spl mu/m parallel multilevel interconnects and its experimental verification","authors":"K. Aoyama, K. Ise, H. Sato, K. Tsuneno, H. Masuda","doi":"10.1109/ICMTS.1995.513946","DOIUrl":null,"url":null,"abstract":"This paper describes a new interconnect design and its verification with test-structures for sub-micron multilevel interconnection. A universal design-chart has been developed, which gives a precise sub-micron interconnect-capacitance for parallel multilevel interconnections. Test-structure measurements show excellent agreement with the design-chart within 4% error. A simple propagation delay model has also been developed.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"76 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings International Conference on Microelectronic Test Structures","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMTS.1995.513946","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
This paper describes a new interconnect design and its verification with test-structures for sub-micron multilevel interconnection. A universal design-chart has been developed, which gives a precise sub-micron interconnect-capacitance for parallel multilevel interconnections. Test-structure measurements show excellent agreement with the design-chart within 4% error. A simple propagation delay model has also been developed.
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