Fast RSFQ and ERSFQ Parallel Counters

Abstract

Historically one of the most challenging high-speed RSFQ circuits to implement has been a parallel counter that sums a set of unweighted inputs and produces a binary-weighted word at the same clock rate. A 7-to-3 parallel counter that sums 7 inputs has been designed and tested at clock frequencies up to 50 GHz using its own dedicated testbed. Yielded in both 10- and 20-kA/cm2 current densities using MIT Lincoln Laboratory's foundry, this 7-to-3 summing circuit has become a digital circuit benchmark. Most recently, a version with 15 parallel inputs producing a 4-bit output was designed using two flavors of 8-to-4 summing circuits. The first (8-to-4a), based on the 7-to-3 parallel counter, sums 8 unweighted inputs whereas the second (8-to-4b) sums two 4-bit binary-weighted words by pairwise summing of bits of equal weights from two 8-to-4a blocks. Design considerations for scaling this circuit will be discussed together with the circuit performance and yield.