A 1.8V 10b 210MS/s CMOS Pipelined ADC Featuring 86dB SFDR without Calibration

Abstract

A 1.8 V 10 b 210 MS/s CMOS pipelined ADC in 0.18 um CMOS process is presented. The low power consumption at high sampling rate is achieved by using an opamp-sharing technique in 2.5 b/stage pipelined ADC architecture. The opamp settling behavior is well controlled through a regulated switch driving scheme. The clever arrangement of capacitor array renders superior SFDR for the same given systematic mismatch. With a 20 MHz input signal, the ADC achieves 85.9 dB SFDR and 9.57 ENOB at 210 MS/s. Better than 76 dB SFDR and 9.5 ENOB performance is maintained for input frequency up to 100 MHz. The ADC core power consumption is 140 mW at 1.8 V supply. The active die area of ADC core is 1.5 mm2.