A BiCMOS technology with 660 MHz vertical PNP transistors for analog/digital ASICs

1989 Proceedings of the IEEE Custom Integrated Circuits Conference Pub Date : 1989-05-15 DOI:10.1109/CICC.1989.56785

K. Soejima, A. Shida, M. Hirata, H. Koga, J. Ukai, H. Sata

引用次数: 6

Abstract

A BiCMOS technology with a triple-diffused vertical p-n-p transistor has been developed to meet wide-bandwidth requirements for mixed analog/digital application-specific integrated circuits (ASICs). An fT of 660 MHz and BVceo of over 15 V were obtained for the p-n-p transistor, by adding only one extra mask to a conventional 2.0-μm BiCMOS process (a total of 20 masks for double-layer metallization). A unity-gain frequency of 52 MHz and DC gain of over 85 dB were obtained for a single-supply operational amplifier with p-n-p first stage. A propagation delay time of 1.27 ns for a CMOS 2 NAND gate has been obtained under a 3 F/O and 3-mm-length wiring load condition

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

用于模拟/数字asic的具有660 MHz垂直PNP晶体管的BiCMOS技术

为了满足混合模拟/数字专用集成电路(asic)的宽带要求，开发了一种具有三扩散垂直p-n-p晶体管的BiCMOS技术。通过在传统的2.0 μm BiCMOS工艺(双层金属化共20个掩模)上增加一个掩模，p-n-p晶体管的fT达到660 MHz, BVceo超过15 V。对于一级p-n-p的单电源运算放大器，获得了52 MHz的单位增益频率和85 dB以上的直流增益。在3f /O和3mm接线负载条件下，CMOS 2 NAND门的传输延迟时间为1.27 ns

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文去求助

来源期刊

1989 Proceedings of the IEEE Custom Integrated Circuits Conference

自引率

0.00%

发文量

期刊最新文献

A 1.4 ns/64 kb RAM with 85 ps/3680 logic gate array A gate matrix deformation and three-dimensional maze routing for dense MOS module generation A submicron CMOS triple level metal technology for ASIC applications Hot carrier effects on CMOS circuit performance The QML-an approach for qualifying ASICs