On using Schmitt trigger for digital logic

Abstract

This paper looks at a classical CMOS NOR-2 gate as well as Schmitt trigger (ST) versions, when the transistors are sized conventionally and unconventionally. ST gates exhibit positive feedback leading to better static noise margins (SNMs), hence less sensitive to noises (i.e., more reliable). The ST concept has lately been used for SRAM cells, with a few papers targeting digital logic. Here we explore the whole voltage and performance range, characterizing SNM, power, delay, and power-delay-product of ST NOR-2 gates, with the aim of getting a better understanding of their advantages for digital logic.