I/sub DDQ/ testing of opens in CMOS SRAMs

Abstract

The behavior of a CMOS SRAM memory in the presence of open defects is analyzed. It has been found that destructive read-out depends on the level of the precharge. Two techniques to test open defects producing data retention faults are proposed. In the first technique an initial condition is forced during the working phase. In this way, intermediate voltages appear during the memorizing phase. Hence, the quiescent current consumption (I/sub DDQ/) increases and the fault can be detected sensing the I/sub DDQ/. A second technique controlling the power supply level in conjunction with sequential access is proposed. This allows detection of open defects by I/sub DDQ/ testing. The cost of both proposed approaches is analyzed.