Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670862
Heebyung Yoon, P. Variyam, A. Chatterjee, N. Nagi
In this paper, we propose a framework for analyzing the effects of circuit parameter variations on high level system specifications in a hierarchical manner. The effects of parameter variations in one level of design hierarchy on those of the next are mapped through linear and piecewise linear sensitivity functions. The models allow computation of the statistical distributions of the circuit parameters and their correlations. This data is used to determine the critical circuit specifications that must be measured and those that may be eliminated from the testing process.
{"title":"Hierarchical statistical inference model for specification based testing of analog circuits","authors":"Heebyung Yoon, P. Variyam, A. Chatterjee, N. Nagi","doi":"10.1109/VTEST.1998.670862","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670862","url":null,"abstract":"In this paper, we propose a framework for analyzing the effects of circuit parameter variations on high level system specifications in a hierarchical manner. The effects of parameter variations in one level of design hierarchy on those of the next are mapped through linear and piecewise linear sensitivity functions. The models allow computation of the statistical distributions of the circuit parameters and their correlations. This data is used to determine the critical circuit specifications that must be measured and those that may be eliminated from the testing process.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123246282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670877
Dinos Moundanos, J. Abraham
Despite great advances in Formal Verification (FV) simulation is still the primary means for design validation. The definition of pragmatic measures for the coverage achieved and the problem of automatic test generation (ATG) are of great importance. In this paper we introduce a new set of metrics, the Event Sequence Coverage Metrics (ESCMs). Our approach is based on an automatic method to extract the control flow of a circuit which can be explored for coverage analysis and ATG. We combine FV and traditional ATPG techniques to automatically generate sequences which traverse uncovered parts of the control graph or exercise uninstantiated control event sequences.
{"title":"Using verification technology for validation coverage analysis and test generation","authors":"Dinos Moundanos, J. Abraham","doi":"10.1109/VTEST.1998.670877","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670877","url":null,"abstract":"Despite great advances in Formal Verification (FV) simulation is still the primary means for design validation. The definition of pragmatic measures for the coverage achieved and the problem of automatic test generation (ATG) are of great importance. In this paper we introduce a new set of metrics, the Event Sequence Coverage Metrics (ESCMs). Our approach is based on an automatic method to extract the control flow of a circuit which can be explored for coverage analysis and ATG. We combine FV and traditional ATPG techniques to automatically generate sequences which traverse uncovered parts of the control graph or exercise uninstantiated control event sequences.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123780940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670842
D. Bhattacharya
The rapid emergence of reusable core-based designs, in the last few years, poses new challenges to the IEEE test access standard 1149.1. Due to widespread industrial acceptance of 1149.1 standard, ICs are now expected to be 1149.1-compliant. At the same time, a typical IC, like the TMS470 microcontroller manufactured by TI, often contains multiple cores with built-in 1149.1 compliant Test Access Port (TAP), as well as significant amounts of non-core logic, which does not have any built-in test access mechanism. In this paper, we present a new TAP design that enables systematic integration of TAP'ed cores with non-TAP'ed logic, and makes the total IC 1149.1 compliant, at the same time. This TAP design, designated Hierarchical Test Access Port (HTAP), has exactly the same I/O pin specifications as an 1149.1-compliant TAP, and can either serve as an 1149.1-compliant TAP, or act as an arbitrator between existing TAPs in the Embedded cores. Behavior of the HTAP-whether to act as a TAP or as an arbitrator of TAPs-is controlled via the TMS input pin.
{"title":"Hierarchical test access architecture for embedded cores in an integrated circuit","authors":"D. Bhattacharya","doi":"10.1109/VTEST.1998.670842","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670842","url":null,"abstract":"The rapid emergence of reusable core-based designs, in the last few years, poses new challenges to the IEEE test access standard 1149.1. Due to widespread industrial acceptance of 1149.1 standard, ICs are now expected to be 1149.1-compliant. At the same time, a typical IC, like the TMS470 microcontroller manufactured by TI, often contains multiple cores with built-in 1149.1 compliant Test Access Port (TAP), as well as significant amounts of non-core logic, which does not have any built-in test access mechanism. In this paper, we present a new TAP design that enables systematic integration of TAP'ed cores with non-TAP'ed logic, and makes the total IC 1149.1 compliant, at the same time. This TAP design, designated Hierarchical Test Access Port (HTAP), has exactly the same I/O pin specifications as an 1149.1-compliant TAP, and can either serve as an 1149.1-compliant TAP, or act as an arbitrator between existing TAPs in the Embedded cores. Behavior of the HTAP-whether to act as a TAP or as an arbitrator of TAPs-is controlled via the TMS input pin.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122438353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670856
V. Champac, J. Castillejos, J. Figueras
The behavior of a CMOS SRAM memory in the presence of open defects is analyzed. It has been found that destructive read-out depends on the level of the precharge. Two techniques to test open defects producing data retention faults are proposed. In the first technique an initial condition is forced during the working phase. In this way, intermediate voltages appear during the memorizing phase. Hence, the quiescent current consumption (I/sub DDQ/) increases and the fault can be detected sensing the I/sub DDQ/. A second technique controlling the power supply level in conjunction with sequential access is proposed. This allows detection of open defects by I/sub DDQ/ testing. The cost of both proposed approaches is analyzed.
{"title":"I/sub DDQ/ testing of opens in CMOS SRAMs","authors":"V. Champac, J. Castillejos, J. Figueras","doi":"10.1109/VTEST.1998.670856","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670856","url":null,"abstract":"The behavior of a CMOS SRAM memory in the presence of open defects is analyzed. It has been found that destructive read-out depends on the level of the precharge. Two techniques to test open defects producing data retention faults are proposed. In the first technique an initial condition is forced during the working phase. In this way, intermediate voltages appear during the memorizing phase. Hence, the quiescent current consumption (I/sub DDQ/) increases and the fault can be detected sensing the I/sub DDQ/. A second technique controlling the power supply level in conjunction with sequential access is proposed. This allows detection of open defects by I/sub DDQ/ testing. The cost of both proposed approaches is analyzed.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122034580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670857
T. Shinogi, T. Hayashi
This paper presents an efficient method for generating a compact test set for IDDQ testing of bridging faults in combinational CMOS circuits. This method is based on the iterative improvement method. Though our method is simple and easy to implement, it is efficient. Experimental results for large ISCAS benchmark circuits demonstrate its efficiency in comparison with results of previous methods.
{"title":"A simple and efficient method for generating compact IDDQ test set for bridging faults","authors":"T. Shinogi, T. Hayashi","doi":"10.1109/VTEST.1998.670857","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670857","url":null,"abstract":"This paper presents an efficient method for generating a compact test set for IDDQ testing of bridging faults in combinational CMOS circuits. This method is based on the iterative improvement method. Though our method is simple and easy to implement, it is efficient. Experimental results for large ISCAS benchmark circuits demonstrate its efficiency in comparison with results of previous methods.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129881433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670845
P. Nordholz, D. Treytnar, J. Otterstedt, H. Grabinski, D. Niggemeyer, T. Williams
The SIA Roadmap shows a very aggressive drive to deep submicron designs. A significant corner stone in the industries' ability to utilize this tremendous capabilities is the usage of reusable cores. When employing cores, one must be sensitive to the quality of the interconnects which will carry signals between cores and the ASIC portion of the network. In this work we will use an extremely accurate line simulator which solves the transmission line equations derived from Maxwell's equations for the simulation of line systems. We will show that the coupling between bus lines is significant, since the signal delay can be increased and even hazards can occur. Furthermore, these effects depend on the set of input signals of all bus lines and the skew between the individual input signals. The lines' cross sections are taken from the SIA Roadmap going from 0.35 /spl mu/m technology design down to 0.10 /spl mu/m technology design.
{"title":"Signal integrity problems in deep submicron arising from interconnects between cores","authors":"P. Nordholz, D. Treytnar, J. Otterstedt, H. Grabinski, D. Niggemeyer, T. Williams","doi":"10.1109/VTEST.1998.670845","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670845","url":null,"abstract":"The SIA Roadmap shows a very aggressive drive to deep submicron designs. A significant corner stone in the industries' ability to utilize this tremendous capabilities is the usage of reusable cores. When employing cores, one must be sensitive to the quality of the interconnects which will carry signals between cores and the ASIC portion of the network. In this work we will use an extremely accurate line simulator which solves the transmission line equations derived from Maxwell's equations for the simulation of line systems. We will show that the coupling between bus lines is significant, since the signal delay can be increased and even hazards can occur. Furthermore, these effects depend on the set of input signals of all bus lines and the skew between the individual input signals. The lines' cross sections are taken from the SIA Roadmap going from 0.35 /spl mu/m technology design down to 0.10 /spl mu/m technology design.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128274662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670866
H. Yotsuyanagi, K. Kinoshita
We present a procedure to reduce sequential circuits by removing undetectable faults based on unreachable states. Procedures for obtaining unreachable stares and for identifying undetectable faults which can be the target of fault removal are presented. Experimental results for ISCAS benchmark circuits are shown.
{"title":"Undetectable fault removal of sequential circuits based on unreachable states","authors":"H. Yotsuyanagi, K. Kinoshita","doi":"10.1109/VTEST.1998.670866","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670866","url":null,"abstract":"We present a procedure to reduce sequential circuits by removing undetectable faults based on unreachable states. Procedures for obtaining unreachable stares and for identifying undetectable faults which can be the target of fault removal are presented. Experimental results for ISCAS benchmark circuits are shown.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130414155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670850
M. Ishida, D. Ha, Takahiro J. Yamaguchi
The overall throughput of automatic test equipment (ATE) is sensitive to the download time of test data. An effective approach to the reduction of the download time is to compress test data before the download. The authors introduced a test data compression method which outperforms other methods for compressing test data. Our previous method was based on the Burrows-Wheeler transformation on the sequence of test patterns and run-length coding. In this paper, we present a new method, called COMPACT, which further improves our previous method. The key idea of COMPACT is to employ two data compression schemes, run-length coding for data with low activity and GZIP for data with high activity. COMPACT increases the compression ratio of test data, on average, by 1.9 times compared with our previous method.
{"title":"COMPACT: a hybrid method for compressing test data","authors":"M. Ishida, D. Ha, Takahiro J. Yamaguchi","doi":"10.1109/VTEST.1998.670850","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670850","url":null,"abstract":"The overall throughput of automatic test equipment (ATE) is sensitive to the download time of test data. An effective approach to the reduction of the download time is to compress test data before the download. The authors introduced a test data compression method which outperforms other methods for compressing test data. Our previous method was based on the Burrows-Wheeler transformation on the sequence of test patterns and run-length coding. In this paper, we present a new method, called COMPACT, which further improves our previous method. The key idea of COMPACT is to employ two data compression schemes, run-length coding for data with low activity and GZIP for data with high activity. COMPACT increases the compression ratio of test data, on average, by 1.9 times compared with our previous method.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123130198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670852
A. P. Stroele
Adders, subtracters, and multipliers, which are available in many data paths, can be utilized to generate patterns and compact test responses. While previous work studied configurations which process patterns and test responses that have the size of a data word, this paper investigates bit serial pattern generators and compactors as they are required, for example, to test a random logic portion of the circuit by means of a scan path. Different arithmetic pattern generators are proposed that can produce a variety of bit strings with long periods and similar fault coverage as pseudorandom bit strings. The paper also analyzes aliasing in arithmetic compactors that process the test responses bit by bit. An upper bound on the limiting value of the aliasing probability for large test lengths can be computed very efficiently. The results of this paper open up a new range of applications for arithmetic BIST.
{"title":"Bit serial pattern generation and response compaction using arithmetic functions","authors":"A. P. Stroele","doi":"10.1109/VTEST.1998.670852","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670852","url":null,"abstract":"Adders, subtracters, and multipliers, which are available in many data paths, can be utilized to generate patterns and compact test responses. While previous work studied configurations which process patterns and test responses that have the size of a data word, this paper investigates bit serial pattern generators and compactors as they are required, for example, to test a random logic portion of the circuit by means of a scan path. Different arithmetic pattern generators are proposed that can produce a variety of bit strings with long periods and similar fault coverage as pseudorandom bit strings. The paper also analyzes aliasing in arithmetic compactors that process the test responses bit by bit. An upper bound on the limiting value of the aliasing probability for large test lengths can be computed very efficiently. The results of this paper open up a new range of applications for arithmetic BIST.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132368286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670905
B. Cockburn, A.L.-C. Kwong
This paper presents simulation evidence supporting the use of bit transition maximization techniques in the design of hardware test pattern generators (TPGs). Bit transition maximization is a heuristic technique that involves increasing the probability that a bit will change values going from one test pattern to the next. For most of the ISCAS-85 benchmarks and many of the ISCAS-89 benchmarks bit transition maximization enhances the fault coverage of two-pattern faults such as gate delay faults and CMOS transistor stuck-open faults. It achieves these benefits without reducing the fault coverage with respect to classical stuck-at faults.
{"title":"Transition maximization techniques for enhancing the two-pattern fault coverage of pseudorandom test pattern generators","authors":"B. Cockburn, A.L.-C. Kwong","doi":"10.1109/VTEST.1998.670905","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670905","url":null,"abstract":"This paper presents simulation evidence supporting the use of bit transition maximization techniques in the design of hardware test pattern generators (TPGs). Bit transition maximization is a heuristic technique that involves increasing the probability that a bit will change values going from one test pattern to the next. For most of the ISCAS-85 benchmarks and many of the ISCAS-89 benchmarks bit transition maximization enhances the fault coverage of two-pattern faults such as gate delay faults and CMOS transistor stuck-open faults. It achieves these benefits without reducing the fault coverage with respect to classical stuck-at faults.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122524645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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