A High-Speed Carry-Select Adder with Optimized Block Sizes

Abstract

A Sarry-Select Adder (CSA) strikes a proper balance between the time delay and area occupation for advanced adder designs. This paper presents a transistor-level circuit implementation of a high-speed CSA, and covers the following design issues: (1) a row of Multiplexer (MUX) is reconfigured in such a way as to increase its operating speed, (2) a conventional add-one circuit is improved to reduce the transistor count, and to eliminate the threshold voltage drop, and (3) a quantity is defined to optimize the block sizes for long word length numbers. Fabricated using TSMC 90-nm CMOS technology, the proposed and a number of published CSAs are simulated for 8, 16, 32 and 64-bit word lengths to validate the performance superiority of this work. In the 64-bit case, the proposed CSA provides an up to 42.1% delay reduction, a 26.1% power reduction, a 57.3% Power-Delay Product (PDP) reduction and a 28.7% transistor count reduction relative to a conventional counterpart.