High speed redundant adder and divider in output prediction logic

Xinyu Guo, C. Sechen
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引用次数: 2

Abstract

A redundant bit adder (RBA) and a divider, both implemented in output prediction logic (OPL), are presented. By combining the carry-free nature of the redundant number system and the high-speed characteristics of OPL, the performance of the arithmetic blocks was tremendously improved. Fabricated in 0.18/spl mu/m/1.8V CMOS, the adder achieves a measured delay of 211ps (2.4 fanout-of-four inverter delays), which is significantly faster than any previously published RBAs. The divider implemented in the same technology can achieve an operating frequency of 1.25GHz.
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输出预测逻辑中的高速冗余加除器
提出了在输出预测逻辑(OPL)中实现的冗余位加法器(RBA)和除法器。将冗余数系统的无携带特性与OPL的高速特性相结合,极大地提高了算法块的性能。该加器采用0.18/spl mu/m/1.8V CMOS制造,实现了211ps的测量延迟(2.4扇出四逆变器延迟),比之前发布的任何rba都要快得多。采用相同技术实现的分频器可以实现1.25GHz的工作频率。
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