Zhu Ming, Wang Tong, Gu Hantian, Qu Ruoyuan, Zhu Hengjing, Z. Wei, Tang Min
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引用次数: 1
Abstract
In this paper, we demonstrate the feasibility and necessity of 3D numerical simulation in the quantitative study of burn-out and latch-up effects in VDMOS and LDMOS power transistors. Insight of which lead to a novel LDMOS layout that is immune to SEL proposed in this paper.
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