Design and analysis of 12.8 Gb/s single-ended signaling for memory interface

Abstract

The design of a high-speed single-ended parallel interface using conventional package and board technologies is presented. The system uses asymmetrical architecture where the equalization and timing adjustment circuits for both memory WRITE and READ transactions are on the controller to reduce the memory cost. The analysis and optimization steps employed to mitigate the effect of inter-symbol interference, crosstalk, and supply noise are discussed. The impact of data encoding techniques on system timing margin is also investigated. The designed single-ended signaling was able to achieve a reliable communication at a data rate of 12.8 Gbps over a graphics channel. Several of the noise reduction techniques were also verified with measurement made on a prototype system.