A Novel High K Inter-poly Dielectric(IPD), A1/sub 2/O/sub 3/ For Low Voltage/high Speed Flash memories: erasing in msecs at 3.3V

Abstract

We propose a novel high K dielectric, A1203 for low voltage/ high speed flash memory without built-in charge pumps. From the analytical modeling, we have quantified the impact of high K IPD and we have verified the feasibility of 10-11 nm A1203 IPD with K-10 for msecs erasing at k3.3V. We have also developed lOnm A1203 films which show the lowest leakage current ever reported for the dielectrics with K>5 [ 131. For the first time, high K dielectric has been demonstrated for high retention f i s h technology. INTRODUCTION In the recent flash memory technologies, short prograderase times and operating voltage reductions are most important issues to realize high speed/low power operation [l-31. In order to accomplish these without a trade-off between low power and high speed operations, high coupling ratio should be achieved by increasing the floating gate capacitance[2,3]. However, decreasing the thickness of IPD to increase the floating gate capacitance may cause serious leakage and reliability problems which are fatal in the retention time of flash memories. Therefore, we focused on the application of high K IPD materials to increase the coupling ratio without cell area increase and complexity of fabrication[6]. In this paper, we present the detail quantification of the impact of IPD dielectric constant on the erasing characteristics of flash memories and A1203 IPD for msecs erasing at 3.3V. We also demonstrate the leakage current characteristics of lOnm A1203 films comparable to those of 20nm ONO and also having the excellent high temperature endurance necessary for flash memory applications [ 1,5]. SIMULATION STRUCTURE To examine the impact of high K IPD, simulations were carried out using the conventional stacked-gate flash cell shown in Fig.1. Gate widthAength was 0.8pm/0.25pm, gate oxide thickness was 5.5nm which was used for low voltage programing and reading[2]. The drain coupling ratio(CFD/COX) was 0.45 and source coupling ratio (CFS/Cox) was 0.05. Fowler-Nordheim (F-N) erasing through the drain and 2volts of threshold voltage shift were assumed. ELECTRIC FIELD ENHANCEMENT BY HIGH R IPD Fig.2 shows the electric fields across gate oxide and IPD as a function of the dielectric constant of IPD layer(K) at the onset of erasing. The gate oxide electric field tends to increase rapidly as K increases and to be saturated after that due to floating gate voltage convergency. In contrast, PPD electric field decreases initially and increases again as K increases due to the positive drain bias and the floating gate charge. This means that, by adopting proper high K IPD materials, the prograderase time can be reduced even at the scaled voltage by maintaininghcreasing the gate oxide ellectric field without poly-poly charge loss. ERASING VOLTAGE AND TIME REDUCTION Fig. 3 shows the control gate voltage reduction ratio to maintain lmsec of erasing time for two different IPD thicknesses as K varies up to 25. About 40% of voltage reduction can be achieved by changing K from 4 to 10. From Fig. 4, we can see about 1OV or higher must be applied between control gate and drain to achieve lmsec of erasing time in case of Si02 IPD. Another thing which should be noticed is that drain bias can reduce the erasing time more effectively than control gate bias. Therefore, large control gate bias reduction can be compensated by small increase in drain bias. Fig. 5 shows the erasing time as a function of K at different drain biases. From this figure, we can see that erasing in less than 100 msecs can be accomplished even at f3.3V of operating voltage, simply by adopting high K IPD material. The application of a lOnm IPD with K-10 can reduce the erasing time by 3 orders of magnitude in comparison with a 15nm ONO IPD(K-5). PROPOSAL OF A1203 FOR FLASH MEMORY IPD For the flash memory application, high K materials must satisfy the following requirements: (a) Low leakage current to guarantee 10 years of retention time. (b) High enough turn-on electric field(25MV/cm) for tunneling to suppress the disturb. (c) High temperature endurance for process integration. We propose A1203 which can meet the above requirements. Fig 6 shows I-V characteristics of 10 nm reactively sputtered A1203 after high temperature furnace annealing and RTA. These films were characterized using RBS, XRD, ellipsometry, and C-V measurements on 500pmx500pm capacitors. These A1203 films showed K of -10, -10MV/cm of breakdown field strength, 25MV/cm of turn-on field for tunneling, and low leakage current comparable to that of 20nm ONO. Fig. 7 shows the leakage current variation after high temperature annealing at several important temperatures for flash integration and the ‘low leakage current is shown to be maintained even after high temperature processes. Even though Ta205 may meet DRAM requirements[4], it is not suitable for high retention non-volatile memory. CONCLUSION We have quantified the impact of high K IPD on erasing characteristics of low voltage/high speed flash memories. e lOnm A1203 IPD with M-10 is shown to reduce the erasing time by 3 orders of magnitude in comparison with 15nm ONO IPD(K-5) and the erasing voltage by 40% compared with Si02 and 27% compared with ONO of the same thickness. *A lOnm A1203 with K-10 for a flash IPD was demonstrated. It showed the lowest leakage current, comparable to a 20nm ONO, which can guarantee long retention time. ACKNOWLEDGEMENT The authors wish to thank E. J. Bower, J. D. Bude, C. Case, S. -e. Chen, E. 9. Laskowski, M. Y. Lau, C. .-Y. Lin, M. A. Marcus, and J. R. Sweeney for their supports and fruitful discussions and W.L. Brown, S. 9. Hillenius, and M. R. Pinto for their supports and encouragements. 117 4-93081 3-75-1 I97 1997 Symposium on VLSl Technology Digest of Technical Papers REFERENCES [ l ] Y. Yamaguchi et al., VLSl Tech. Symp, p.85, 1!>93 [2] J. D. Bude et al., Tech.Dig. of IEDM, p. 989, 1995 [3] S. Ueno et al., VLSI Tech. Symp, p.54, 1996 [4] Y. Takashi et al., Tech.Dig. of IEDM, p. 839, 1994 [5] S. Mori et al., IEEE Trans. Electron Devices, Vol. 38, No. 2, [6] H. Shirai et al., Tech.Dig. of lEDM, p. 653, 1995 p. 270, 1991.