{"title":"An X- and Ku-Band 8-Element Linear Phased Array Receiver","authors":"Kwang-Jin Koh, Gabriel M. Rebeiz","doi":"10.1109/CICC.2007.4405841","DOIUrl":null,"url":null,"abstract":"This paper presents an 8-element linear phased array receiver in 0.18-mum SiGe BiCMOS technology for X-and Ku-band applications. The array receiver adopts RF phase shifting architecture and the active 4-bit phase shifter synthesizes a phase by adding two properly weighted I-and Q-input. With all the digital control circuitry, bandgap reference and ESD protection for all I/O pads, the receiver consumes 170 mA from a 3.3 V supply voltage. The receiver shows about 20 dB of power gain per channel at 12 GHz with a 3-dB gain bandwidth from 8.5 to 14.5 GHz. The rms gain error is less than 0.9 dB and the rms phase error is less than 6deg at 6-18 GHz for all the 4-bit phase states. The minimum NF is 3.85 dB at 10-11 GHz and typical input PldB at 12 GHz is -31 dBm. The overall chip size is 2.2times2.45 mm2. To our knowledge, this is the first demonstration of an RF-based phased array in a silicon chip with the record rms phase and gain errors at 6-18 GHz.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"28","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2007.4405841","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 28
Abstract
This paper presents an 8-element linear phased array receiver in 0.18-mum SiGe BiCMOS technology for X-and Ku-band applications. The array receiver adopts RF phase shifting architecture and the active 4-bit phase shifter synthesizes a phase by adding two properly weighted I-and Q-input. With all the digital control circuitry, bandgap reference and ESD protection for all I/O pads, the receiver consumes 170 mA from a 3.3 V supply voltage. The receiver shows about 20 dB of power gain per channel at 12 GHz with a 3-dB gain bandwidth from 8.5 to 14.5 GHz. The rms gain error is less than 0.9 dB and the rms phase error is less than 6deg at 6-18 GHz for all the 4-bit phase states. The minimum NF is 3.85 dB at 10-11 GHz and typical input PldB at 12 GHz is -31 dBm. The overall chip size is 2.2times2.45 mm2. To our knowledge, this is the first demonstration of an RF-based phased array in a silicon chip with the record rms phase and gain errors at 6-18 GHz.