Strain Engineering in Modern Si Trench Power MOSFETs — A Performance Booster for Future Generations

Abstract

The ongoing trend towards electrification and digitalization requires the continuous improvement of high frequency, high power density switching solutions such as split-gate Si trench power MOSFETs. However, their pure figure of merit (FOM) related performance improvement through conventional scaling has reached a physical limit. Similar to the approaches for planar MOSFETs, the device performance can also be improved by strain engineering, leading to a modified charge carrier mobility in the electrically active monocrystalline Si. Therefore, a novel strain engineering approach is proposed for Si trench power MOSFETs, adding a strain functionality to the trenches on top of their charge compensation purpose. It is shown that the device performance is increased by up to 16.8%, which is achieved by not only altering the mobility in the channel but also influencing the drift region of the device. Since the correlation of electrical and mechanical device characteristics is key to effectively implement strain engineering concepts in Si trench power MOSFETs, high-precision nanoscale stress and strain characterization techniques as well as finite element mechanical simulations are established and presented.