A low-power 0.7-V H.264 720p video decoder

Abstract

The H.264/AVC video coding standard can deliver high compression efficiency at a cost of large complexity and power. The increasing popularity of video capture and playback on portable devices requires that the energy of the video codec be kept to a minimum. This paper proposes several architecture optimizations such as increased parallelism, multiple voltage/frequency domains, and custom voltage-scalable SRAMs that enable low voltage operation and reduce the power of a high-definition decoder. An H.264/AVC Baseline Level 3.1 decoder ASIC was fabricated in 65 nm CMOS and verified. It operates down to 0.7-V and has a measured power of 1.8 mW when decoding a high definition 720 p video at 30 frames per second, which is over an order of magnitude lower than previously published results.