{"title":"A low-power auto-zeroed comparator for column-paralleled 14b SAR ADCs of 384×288 IRFPA ROIC","authors":"Meng Chen, Wengao Lu, Tingting Tao, Yacong Zhang, Zhongjian Chen","doi":"10.1109/EDSSC.2013.6628037","DOIUrl":null,"url":null,"abstract":"This paper presents a low power comparator with auto-zeroed technique for the readout chain of a 384×288 infrared focal plane array (IRFPA). To overcome the high power consumption of column-paralleled application, a novel inverter=based pre-amplifier is introduced. The performances of the proposed comparator are verified by a 14-bit column paralleled Successive-Approximation-Register (SAR) A/D converter which is developed in a 0.35um CMOS-based process technology. The SFDR of the A/D converter is up to 93dB at a sampling clock of 31.25 KHz with an input signal of 1.009 KHz. The overall static power of the 384 column-paralleled ADCs is less than 50mW.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2013.6628037","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper presents a low power comparator with auto-zeroed technique for the readout chain of a 384×288 infrared focal plane array (IRFPA). To overcome the high power consumption of column-paralleled application, a novel inverter=based pre-amplifier is introduced. The performances of the proposed comparator are verified by a 14-bit column paralleled Successive-Approximation-Register (SAR) A/D converter which is developed in a 0.35um CMOS-based process technology. The SFDR of the A/D converter is up to 93dB at a sampling clock of 31.25 KHz with an input signal of 1.009 KHz. The overall static power of the 384 column-paralleled ADCs is less than 50mW.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
