H. Uda, T. Hirai, H. Tominaga, K. Nogawa, T. Sawai, S. Higashino, Y. Harada
{"title":"A very high isolation GaAs SPDT switch IC sealed in an ultra compact plastic package","authors":"H. Uda, T. Hirai, H. Tominaga, K. Nogawa, T. Sawai, S. Higashino, Y. Harada","doi":"10.1109/GAAS.1995.528978","DOIUrl":null,"url":null,"abstract":"A high-isolation switch IC with 31 dB isolation and 0.88 dB insertion loss at 1.65 GHz, sealed in a 6-pin ultra-compact plastic package having approximately 1/4 the conventional area, was developed for the first time. An electromagnetic-field simulation analysis of the isolation characteristics between the lead pins of the ultra-compact package was used for this IC together with a new design method which takes into account deterioration of the isolation characteristics due to the plastic molding. Electromagnetic-field simulation was also used in the layout design to minimize chip size.","PeriodicalId":422183,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GAAS.1995.528978","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
A high-isolation switch IC with 31 dB isolation and 0.88 dB insertion loss at 1.65 GHz, sealed in a 6-pin ultra-compact plastic package having approximately 1/4 the conventional area, was developed for the first time. An electromagnetic-field simulation analysis of the isolation characteristics between the lead pins of the ultra-compact package was used for this IC together with a new design method which takes into account deterioration of the isolation characteristics due to the plastic molding. Electromagnetic-field simulation was also used in the layout design to minimize chip size.