Synthesis approach to multi-level regular representation for combinational circuits

Abstract

In this paper we present a new approach to the synthesis of regular two-dimensional, multilevel logic arrays. We address a new restricted factorization method to synthesis a combinational function as a two-dimensional multi-level array. This is an integrated logic and layout synthesis method which can be used for full custom design such as module generation or for locally-connected fine-grain FPGAs. We defined a new multi-bus architecture, and developed an algorithm to solve the synthesis problem. The benchmark results show encouraging improvements over previous approaches.