Elevated temperature plasma doping technology for sub-50 nm SOI n-MOSFETs

Abstract

A novel plasma doping technique for fabricating a nano-scale silicon-on-insulator (SOI) MOSFETs have been investigated. The S/D extensions of the tri-gate structure. SOI n-MOSFETs were formed by using elevated temperature plasma doping method. The activation annealing after plasma doping was excluded to minimize the diffusion of dopants, which resulted in laterally abrupt S/D junction. We obtained low damage shallow junctions and sheet resistance of 920 /spl Omega/ //spl square/ by the elevated temperature plasma doping of 527/spl deg/C. A tri-gate structure SOT n-MOSFET with a gate length of Sub-50 nm was successfully fabricated and revealed suppressed short channel effects.