Gate length impact on UTBOX FBRAM devices

Abstract

FBRAM on UTBOX SOI wafers, using the BJT with a positive back bias programming scheme, is studied versus the gate length. The optimized FBRAM parameters such as the sense margin and the retention time are shown as a function of the gate length. For longer L the back bias can be used to optimize the FBRAM performance, whereas for shorter L, hole generation amplification during the read operation by the bipolar junction transistor gain, inherent to SOI nMOSFET devices and used for the read is a limiting issue. Therefore, there is critical gate length to FBRAM scaling. To avoid FBRAM performance degradation, L should be longer than the critical length. Moreover, this work suggests that vertical devices, which allow longer L are more scalable.