Pub Date : 2012-12-01DOI: 10.1109/SOI.2012.6404352
C. Hu, A. Niknejad, V. Sriramkumar, D. Lu, Y. Chauhan, M. Kahm, A. Sachid
□ BSIM-IMG is a Turnkey, Production Ready model □ Will be submitted to the CMC for standardization □ Physical, Scalable Core Model for FDSOI devices □ Plethora of Real Device Effects modeled □ Advanced Device Effects — Quantum, Back-gate bias, Self-heating □ Validated on Hardware Data from two FDSOI/ UTBSOI technologies □ Available in major EDA tools.
{"title":"BSIM-IMG: A Turnkey compact model for fully depleted technologies","authors":"C. Hu, A. Niknejad, V. Sriramkumar, D. Lu, Y. Chauhan, M. Kahm, A. Sachid","doi":"10.1109/SOI.2012.6404352","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404352","url":null,"abstract":"□ BSIM-IMG is a Turnkey, Production Ready model □ Will be submitted to the CMC for standardization □ Physical, Scalable Core Model for FDSOI devices □ Plethora of Real Device Effects modeled □ Advanced Device Effects — Quantum, Back-gate bias, Self-heating □ Validated on Hardware Data from two FDSOI/ UTBSOI technologies □ Available in major EDA tools.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117267289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/SOI.2012.6404396
M. Saitoh, K. Ota, C. Tanaka, K. Uchida, T. Numata
We demonstrated high-Ion and small-σVth 10nm-NW Tr. wth SMT. Tri-gate NW structures with small HNW and thin BOX offer high Vth tunability by Vsub. SOI tri-gate NW Tr. presented in this work is a key device in future ultralow-power CMOS LSI.
{"title":"SOI tri-gate nanowire MOSFETs for ultra-low power LSI","authors":"M. Saitoh, K. Ota, C. Tanaka, K. Uchida, T. Numata","doi":"10.1109/SOI.2012.6404396","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404396","url":null,"abstract":"We demonstrated high-I<sub>on</sub> and small-σV<sub>th</sub> 10nm-NW Tr. wth SMT. Tri-gate NW structures with small HNW and thin BOX offer high Vth tunability by Vsub. SOI tri-gate NW Tr. presented in this work is a key device in future ultralow-power CMOS LSI.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"174 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123475150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404385
A. Joshi, S. Lee, Y. Y. Chen, T. Y. Lee
In recent years, CMOS on Silicon-on-Insulator has rapidly evolved as a mainstream technology for switches used in wireless applications. Since such applications can involve switching high power levels (35 dBm) at high frequencies (~2 GHz), the technology considerations are substantially different than those for SOI used in high speed, small signal applications such as microprocessors. This paper provides an overview of key technology challenges and trade-offs.
{"title":"Optimized CMOS-SOI process for high performance RF switches","authors":"A. Joshi, S. Lee, Y. Y. Chen, T. Y. Lee","doi":"10.1109/SOI.2012.6404385","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404385","url":null,"abstract":"In recent years, CMOS on Silicon-on-Insulator has rapidly evolved as a mainstream technology for switches used in wireless applications. Since such applications can involve switching high power levels (35 dBm) at high frequencies (~2 GHz), the technology considerations are substantially different than those for SOI used in high speed, small signal applications such as microprocessors. This paper provides an overview of key technology challenges and trade-offs.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"206 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123057697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404355
Y. Morita, T. Mori, S. Migita, W. Mizubayashi, A. Tanabe, K. Fukuda, M. Masahara, H. Ota
CMOS tunnel FETs (TFETs) with vertical-tunnel-multiplication (VTM) were fabricated. VTM TFETs initiate band-to-band tunneling (BTBT) parallel to the gate electric field and effectively extend the tunnel area. Impact of the VTM was analyzed using a distributed-element circuit model, and the drain current multiplication by extended tunnel area was experimentally revealed for the first time.
{"title":"First demonstration of drain current enhancement in SOI tunnel FET with vertical-tunnel-multiplication","authors":"Y. Morita, T. Mori, S. Migita, W. Mizubayashi, A. Tanabe, K. Fukuda, M. Masahara, H. Ota","doi":"10.1109/SOI.2012.6404355","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404355","url":null,"abstract":"CMOS tunnel FETs (TFETs) with vertical-tunnel-multiplication (VTM) were fabricated. VTM TFETs initiate band-to-band tunneling (BTBT) parallel to the gate electric field and effectively extend the tunnel area. Impact of the VTM was analyzed using a distributed-element circuit model, and the drain current multiplication by extended tunnel area was experimentally revealed for the first time.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117219167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404373
Sang Wan Kim, W. Choi, Min-Chul Sun, H. Kim, Byung-Gook Park
L-shaped tunneling field-effect transistors (TFETs) feature high current drivability and abrupt on-off transition. For further improvement of L-shaped TFETs, tunneling regions become n-type doped in this study. The doping concentration of the tunneling regions is optimized. The proposed novel L-shaped TFETs show higher on-current (Ion) and lower subthreshold swing (SS) than conventional L-shaped TFETs.
{"title":"Design improvement of L-shaped tunneling field-effect transistors","authors":"Sang Wan Kim, W. Choi, Min-Chul Sun, H. Kim, Byung-Gook Park","doi":"10.1109/SOI.2012.6404373","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404373","url":null,"abstract":"L-shaped tunneling field-effect transistors (TFETs) feature high current drivability and abrupt on-off transition. For further improvement of L-shaped TFETs, tunneling regions become n-type doped in this study. The doping concentration of the tunneling regions is optimized. The proposed novel L-shaped TFETs show higher on-current (Ion) and lower subthreshold swing (SS) than conventional L-shaped TFETs.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122334723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404367
A. Sachid, C. Hu
There is a difference in the nature of parasitic capacitance with electrical width of planar MOSFET and FinFET. This difference can be used to optimize FinFET circuits to achieve lower power dissipation and power density compared to planar MOSFET circuits. To achieve the best results, circuits should be re-optimized considering the parasitics before replacing planar MOSFETs with FinFETs.
{"title":"A little known benefit of FinFET over Planar MOSFET in highperformance circuits at advanced technology nodes","authors":"A. Sachid, C. Hu","doi":"10.1109/SOI.2012.6404367","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404367","url":null,"abstract":"There is a difference in the nature of parasitic capacitance with electrical width of planar MOSFET and FinFET. This difference can be used to optimize FinFET circuits to achieve lower power dissipation and power density compared to planar MOSFET circuits. To achieve the best results, circuits should be re-optimized considering the parasitics before replacing planar MOSFETs with FinFETs.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124032614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404370
D. Bol, V. Kilchytska, J. De Vos, F. Andrieu, D. Flandre
Power-gating enables low stand-by power for high-speed applications. In this paper, we exploit the unique feature of quasi-double gate (QDG) mode MOSFETs in UTBB SOI to boost the performances of the power-gating sleep transistor. According to experimental results on a 10-nm BOX, at nominal Vg QDG mode enables up to 35% width and thereby leakage reduction for the sleep transistor. At circuit level, a charge pump architecture is proposed to generate the QDG back-gate bias for a 100-mA power-gated CPU with sub-100 ns wake-up/sleep times and negligible power/area overheads.
{"title":"Quasi-double gate mode for sleep transistors in UTBB FD SOI low-power high-speed applications","authors":"D. Bol, V. Kilchytska, J. De Vos, F. Andrieu, D. Flandre","doi":"10.1109/SOI.2012.6404370","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404370","url":null,"abstract":"Power-gating enables low stand-by power for high-speed applications. In this paper, we exploit the unique feature of quasi-double gate (QDG) mode MOSFETs in UTBB SOI to boost the performances of the power-gating sleep transistor. According to experimental results on a 10-nm BOX, at nominal Vg QDG mode enables up to 35% width and thereby leakage reduction for the sleep transistor. At circuit level, a charge pump architecture is proposed to generate the QDG back-gate bias for a 100-mA power-gated CPU with sub-100 ns wake-up/sleep times and negligible power/area overheads.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122006443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404401
K. Yoo, D. Lee, R. Tiberio, J. Conway, H. Wong, Y. Nishi
This paper reports the design optimization of lateral nanoelectromechanical (NEM) relays for sub 1V actuation by COMSOL simulation with various materials and structures. Measured actuation voltages from fabricated relays showed good matching with simulation.
{"title":"Design and materials selection for low power laterally actuating nanoelectromechanical relays","authors":"K. Yoo, D. Lee, R. Tiberio, J. Conway, H. Wong, Y. Nishi","doi":"10.1109/SOI.2012.6404401","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404401","url":null,"abstract":"This paper reports the design optimization of lateral nanoelectromechanical (NEM) relays for sub 1V actuation by COMSOL simulation with various materials and structures. Measured actuation voltages from fabricated relays showed good matching with simulation.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128200291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404379
R. Doria, R. Trevisoli, M. de Souza, I. Ferain, S. Das, M. Pavanello
This work presented an experimental analysis of the LFN in p and n-type JNTs of different L and doping concentrations. JNTs have shown 1/f noise as the main noise component, which has been associated to CNF in nMOS and MF in the pMOS. Also, SId reduced with the rise of the doping concentration and with the raise of L.
{"title":"Low-Frequency Noise of nMOS and pMOS short channel junctionless nanowire transistors","authors":"R. Doria, R. Trevisoli, M. de Souza, I. Ferain, S. Das, M. Pavanello","doi":"10.1109/SOI.2012.6404379","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404379","url":null,"abstract":"This work presented an experimental analysis of the LFN in p and n-type JNTs of different L and doping concentrations. JNTs have shown 1/f noise as the main noise component, which has been associated to CNF in nMOS and MF in the pMOS. Also, SId reduced with the rise of the doping concentration and with the raise of L.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133268045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404357
G. Patton
□ SOI has enabled industry leadership in planar CMOS exemplified by both digital and analog mixed-signal applications □ Innovative future opportunities for SOI as Industry moves to Fully Depleted Architectures and beyond Uniformity and Variability control are at the forefront! □ Paradigm shift in SOI value proposition as FinFET era arrives.
{"title":"Evolution and expansion of SOI in VLSI technologies: Planar to 3D","authors":"G. Patton","doi":"10.1109/SOI.2012.6404357","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404357","url":null,"abstract":"□ SOI has enabled industry leadership in planar CMOS exemplified by both digital and analog mixed-signal applications □ Innovative future opportunities for SOI as Industry moves to Fully Depleted Architectures and beyond Uniformity and Variability control are at the forefront! □ Paradigm shift in SOI value proposition as FinFET era arrives.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126053856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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