A high density matched hexagonal transistor structure in standard CMOS technology for high speed applications

Abstract

In this paper, a very dense CMOS hexagonal transistor structure is presented. The main advantages of the transistors are the low parasitic drain and source capacitance due to the small area. The matching properties of this structure have been investigated and these results have been compared to those for traditional finger style structures. Exploiting these advantages, these transistors are very well suited for high speed applications with a demand for both good matching and small area, such as e.g. multi-bit current steering D/A converters. The test chips have been implemented in a standard 0.5 /spl mu/m CMOS technology. No adaptations to the technology have been made in order to realize the structures.