Pub Date : 1999-03-15DOI: 10.1109/ICMTS.1999.766244
J. Vildeuil, M. Valenza, D. Rigaud
1/f noise is investigated in a set of transistors issued from a 0.8 /spl mu/m CMOS technology. Measurements have been analysed versus gate and drain biases. Noise parameters for BSIM3 simulation are extracted in all operating regions using a new extraction procedure. As expected, three noise parameters (NOIA, NOIB and NOIC) can model the noise in all operating regimes. Moreover, it is shown that for the studied transistors, the contribution of NOIC is neglible in the saturation range. Some inaccuracies of the BSIM3v3 noise model are pointed out; in particular, the experimental data indicates that for n-channel MOSFETs, the NOIB parameter is V/sub GS/-V/sub T/ dependent.
{"title":"CMOS 1/f noise modelling and extraction of BSIM3 parameters using a new extraction procedure","authors":"J. Vildeuil, M. Valenza, D. Rigaud","doi":"10.1109/ICMTS.1999.766244","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766244","url":null,"abstract":"1/f noise is investigated in a set of transistors issued from a 0.8 /spl mu/m CMOS technology. Measurements have been analysed versus gate and drain biases. Noise parameters for BSIM3 simulation are extracted in all operating regions using a new extraction procedure. As expected, three noise parameters (NOIA, NOIB and NOIC) can model the noise in all operating regimes. Moreover, it is shown that for the studied transistors, the contribution of NOIC is neglible in the saturation range. Some inaccuracies of the BSIM3v3 noise model are pointed out; in particular, the experimental data indicates that for n-channel MOSFETs, the NOIB parameter is V/sub GS/-V/sub T/ dependent.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128222988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-15DOI: 10.1109/ICMTS.1999.766219
L. Kasel, C. McAndrew, P. Drennan, W.F. Davis, R. Ida
This paper presents procedures and software tools for automatic generation of test masks, and mask and measurement databases, for SPICE model characterization. The process uses Cadence Pcells, and requires user specification only of a small amount of biasing information. The tools generate device instances, place and route the devices, extract test array coordinates and contents from layout for auto-probing, generate measurement test plans, and generate test mask documentation.
{"title":"Automated generation of SPICE characterization test masks and test databases","authors":"L. Kasel, C. McAndrew, P. Drennan, W.F. Davis, R. Ida","doi":"10.1109/ICMTS.1999.766219","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766219","url":null,"abstract":"This paper presents procedures and software tools for automatic generation of test masks, and mask and measurement databases, for SPICE model characterization. The process uses Cadence Pcells, and requires user specification only of a small amount of biasing information. The tools generate device instances, place and route the devices, extract test array coordinates and contents from layout for auto-probing, generate measurement test plans, and generate test mask documentation.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124229331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-15DOI: 10.1109/ICMTS.1999.766242
D. MacSweeney, K. McCarthy, A. Mathewson, J. A. Power, S. C. Kelly
In this paper, the effect of the substrate interaction is examined for the R/sub E/ flyback method which is commonly used to measure the emitter resistance of BJT devices. By considering the structure to be a combination of two devices, the measurement conditions can be understood better for different substrate configurations, giving improved confidence in the method.
{"title":"Inclusion of substrate effects in the flyback method for BJT resistance characterisation","authors":"D. MacSweeney, K. McCarthy, A. Mathewson, J. A. Power, S. C. Kelly","doi":"10.1109/ICMTS.1999.766242","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766242","url":null,"abstract":"In this paper, the effect of the substrate interaction is examined for the R/sub E/ flyback method which is commonly used to measure the emitter resistance of BJT devices. By considering the structure to be a combination of two devices, the measurement conditions can be understood better for different substrate configurations, giving improved confidence in the method.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114743278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-15DOI: 10.1109/ICMTS.1999.766237
S. Foley, J. Molyneaux, A. Mathewson
A number of fast wafer level test methods exist for interconnect reliability evaluation. The relative abilities of three such methods to predict the quality and reliability of the interconnect over very short test times are evaluated in this work. Four different test structure designs are also evaluated and the results are compared with package level median time to failure (MTF) results. The isothermal test method combined with SWEAT-type (standard wafer-level electromigration accelerated test) structures is shown to be the most suitable combination for interconnect reliability detection and control over very short test times.
{"title":"Evaluation of test methods and associated test structures for interconnect reliability control","authors":"S. Foley, J. Molyneaux, A. Mathewson","doi":"10.1109/ICMTS.1999.766237","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766237","url":null,"abstract":"A number of fast wafer level test methods exist for interconnect reliability evaluation. The relative abilities of three such methods to predict the quality and reliability of the interconnect over very short test times are evaluated in this work. Four different test structure designs are also evaluated and the results are compared with package level median time to failure (MTF) results. The isothermal test method combined with SWEAT-type (standard wafer-level electromigration accelerated test) structures is shown to be the most suitable combination for interconnect reliability detection and control over very short test times.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126109267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-15DOI: 10.1109/ICMTS.1999.766223
Seonghearn Lee, Hyun-Kyu Yu
A new parameter extraction technique utilizing S-parameter data at the GHz range is proposed for a SPICE BSIM3v3 model of an RF MOSFET. The extraction of capacitance parameters is carried out using S-parameter sets measured under specific bias conditions for various device sizes. The resistances (R/sub g/, R/sub d/) and inductances are obtained by fitting the frequency responses of Z-parameter equations, and source and substrate resistances are determined using S-parameter optimization. Good correspondence is observed between measured and modeled S-parameters up to 12 GHz.
{"title":"A new extraction method for BSIM3v3 model parameters of RF silicon MOSFETs","authors":"Seonghearn Lee, Hyun-Kyu Yu","doi":"10.1109/ICMTS.1999.766223","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766223","url":null,"abstract":"A new parameter extraction technique utilizing S-parameter data at the GHz range is proposed for a SPICE BSIM3v3 model of an RF MOSFET. The extraction of capacitance parameters is carried out using S-parameter sets measured under specific bias conditions for various device sizes. The resistances (R/sub g/, R/sub d/) and inductances are obtained by fitting the frequency responses of Z-parameter equations, and source and substrate resistances are determined using S-parameter optimization. Good correspondence is observed between measured and modeled S-parameters up to 12 GHz.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129406126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-15DOI: 10.1109/ICMTS.1999.766226
G. Ghibaudo, S. Bruyère, T. Devoivre, B. Desalvo, E. Vincent
An improved method for the assessment of the oxide thickness applicable to advanced CMOS technologies is proposed. To this end, a proper combination of Maserjian's technique (Maserjian et al., Solid State Electron. vol. 17, pp. 335-9, 1974) and of Vincent's method (Vincent et al., Proc. IEEE Microelectronic Test Structures vol. 10, pp. 105-10, 1997) is used to alleviate the unknown parameter inherent to both extraction procedures and which depends on the employed carrier statistics. The new method has been successfully applied to various technologies with gate oxide thickness ranging from 7 nm down to 1.8 nm.
提出了一种适用于先进CMOS技术的评价氧化层厚度的改进方法。为此，适当地结合Maserjian的技术(Maserjian et al.， Solid State Electron。vol. 17, pp. 335-9, 1974)和Vincent的方法(Vincent等人，Proc. IEEE微电子测试结构vol. 10, pp. 105-10, 1997)被用来减轻提取过程中固有的未知参数，这取决于所使用的载波统计。该方法已成功应用于栅极氧化层厚度从7 nm到1.8 nm的各种工艺中。
{"title":"Improved method for the oxide thickness extraction in MOS structures with ultra-thin gate dielectrics","authors":"G. Ghibaudo, S. Bruyère, T. Devoivre, B. Desalvo, E. Vincent","doi":"10.1109/ICMTS.1999.766226","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766226","url":null,"abstract":"An improved method for the assessment of the oxide thickness applicable to advanced CMOS technologies is proposed. To this end, a proper combination of Maserjian's technique (Maserjian et al., Solid State Electron. vol. 17, pp. 335-9, 1974) and of Vincent's method (Vincent et al., Proc. IEEE Microelectronic Test Structures vol. 10, pp. 105-10, 1997) is used to alleviate the unknown parameter inherent to both extraction procedures and which depends on the employed carrier statistics. The new method has been successfully applied to various technologies with gate oxide thickness ranging from 7 nm down to 1.8 nm.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129686924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-15DOI: 10.1109/ICMTS.1999.766233
M. Linder, F. Ingvarson, K. Jeppson, J. Grahn, S. Zhang, M. Ostling
A new procedure for direct extraction of the base and emitter resistances is presented. The parameters are extracted from a single measurement on a transistor test structure with two separated base contacts. The proposed extraction procedure was successfully applied to transistors fabricated in a double polysilicon bipolar transistor process and a commercial 0.8 /spl mu/m single polysilicon BiCMOS process. The extracted values show good agreement with those obtained by means of high frequency measurements. Furthermore, the method was verified by simulations and extraction from modelled data using a distributed resistor-diode transistor model. Both emitter current crowding effects and conductivity modulation in the base are considered in the model. The comparison between measured and modelled transistor characteristics using the extracted values as input in the Gummel-Poon model also validates the DC extraction method. The method was found to be valid as long as conductivity modulation in the base is dominant over emitter current crowding effects as a cause for the decrease in the base resistance.
{"title":"A new procedure for extraction of series resistances for bipolar transistors from DC measurements","authors":"M. Linder, F. Ingvarson, K. Jeppson, J. Grahn, S. Zhang, M. Ostling","doi":"10.1109/ICMTS.1999.766233","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766233","url":null,"abstract":"A new procedure for direct extraction of the base and emitter resistances is presented. The parameters are extracted from a single measurement on a transistor test structure with two separated base contacts. The proposed extraction procedure was successfully applied to transistors fabricated in a double polysilicon bipolar transistor process and a commercial 0.8 /spl mu/m single polysilicon BiCMOS process. The extracted values show good agreement with those obtained by means of high frequency measurements. Furthermore, the method was verified by simulations and extraction from modelled data using a distributed resistor-diode transistor model. Both emitter current crowding effects and conductivity modulation in the base are considered in the model. The comparison between measured and modelled transistor characteristics using the extracted values as input in the Gummel-Poon model also validates the DC extraction method. The method was found to be valid as long as conductivity modulation in the base is dominant over emitter current crowding effects as a cause for the decrease in the base resistance.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128503939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-15DOI: 10.1109/ICMTS.1999.766218
M. Graziano, G. Masera, G. Piccinini, M. Ruo Roch, M. Zamboni
Technology downscaling and high performance architectures are the main trends in high speed CMOS VLSI circuits. These two factors require respectively increasing device integration and the design of new dynamic logic families for high level pipelining structures. An increasingly pressing problem connected to this trend is crosstalk noise between interconnections and self-induced noise due to simultaneous switching of large numbers of gates. A test IC was realized for noise tolerance measurement of high speed CMOS logic families. Variable energy noise events are internally generated using integrated inductors that switch according to a programmable combination of control signals. The effects of the injected noise are measured in terms of logic errors by a detection structure: a statistic for the measured outputs is created and compared with the results of a simulation tool for the evaluation of noise tolerance in CMOS logic families.
{"title":"A statistical noise-tolerance analysis and test structure for logic families","authors":"M. Graziano, G. Masera, G. Piccinini, M. Ruo Roch, M. Zamboni","doi":"10.1109/ICMTS.1999.766218","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766218","url":null,"abstract":"Technology downscaling and high performance architectures are the main trends in high speed CMOS VLSI circuits. These two factors require respectively increasing device integration and the design of new dynamic logic families for high level pipelining structures. An increasingly pressing problem connected to this trend is crosstalk noise between interconnections and self-induced noise due to simultaneous switching of large numbers of gates. A test IC was realized for noise tolerance measurement of high speed CMOS logic families. Variable energy noise events are internally generated using integrated inductors that switch according to a programmable combination of control signals. The effects of the injected noise are measured in terms of logic errors by a detection structure: a statistic for the measured outputs is created and compared with the results of a simulation tool for the evaluation of noise tolerance in CMOS logic families.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"2017 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128733621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-15DOI: 10.1109/ICMTS.1999.766213
S. Van den Bosch, W. De Ketalaere, L. Martens
For the first time, four devices proposed in the literature for noise measurement verification are compared on the same basis. We present measured and simulated standard deviations of extracted noise parameters, taking into account S-parameter errors of the entire set-up, with the introduction of an improved method to account for S-parameter errors in statistical simulations. We conclude that multiple devices should be used for verification.
{"title":"Comparison of micro-electronic test structures for noise measurement verification","authors":"S. Van den Bosch, W. De Ketalaere, L. Martens","doi":"10.1109/ICMTS.1999.766213","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766213","url":null,"abstract":"For the first time, four devices proposed in the literature for noise measurement verification are compared on the same basis. We present measured and simulated standard deviations of extracted noise parameters, taking into account S-parameter errors of the entire set-up, with the introduction of an improved method to account for S-parameter errors in statistical simulations. We conclude that multiple devices should be used for verification.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127263482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-03-15DOI: 10.1109/ICMTS.1999.766216
O. Paul, L. Plattner, H. Baltes
A micromachined thermal van der Pauw test structure is reported. Similar in principle to the conventional electrical van der Pauw Greek cross test structures, it enables the in-plane thermal sheet conductivities of thin films to be determined. The analogy between the two-dimensional heat flow in thin film samples and the electrical current pattern in thin film conductors is exploited. A thermal sheet resistance of 1.87/spl times/10/sup 5/ K/W was extracted from the complete sandwich of dielectric layers of a commercial CMOS ASIC process. This is equivalent to an average in-plane thermal conductivity of the CMOS dielectric layer sandwich of /spl kappa/=1.44 Wm/sup -1/ K/sup -1/.
{"title":"A thermal van der Pauw test structure","authors":"O. Paul, L. Plattner, H. Baltes","doi":"10.1109/ICMTS.1999.766216","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766216","url":null,"abstract":"A micromachined thermal van der Pauw test structure is reported. Similar in principle to the conventional electrical van der Pauw Greek cross test structures, it enables the in-plane thermal sheet conductivities of thin films to be determined. The analogy between the two-dimensional heat flow in thin film samples and the electrical current pattern in thin film conductors is exploited. A thermal sheet resistance of 1.87/spl times/10/sup 5/ K/W was extracted from the complete sandwich of dielectric layers of a commercial CMOS ASIC process. This is equivalent to an average in-plane thermal conductivity of the CMOS dielectric layer sandwich of /spl kappa/=1.44 Wm/sup -1/ K/sup -1/.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128790757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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