A Rail-to-Rail CMOS Voltage Comparator with Programmable Hysteresis

Abstract

A low offset voltage comparator with programmable hysteresis is analyzed, simulated, and presented. The comparator employs a new method for creating the hysteresis and its low-to-high and high-to-low transition threshold levels can be controlled independently even after fabrication. The circuit uses an NMOS and a PMOS preamplifier to accomplish the rail-to-rail operation. The comparator is designed and simulated in a conventional $0.13-\mu\mathrm{m}$ CMOS process with a 3.3-V supply voltage. Monte Carlo simulations show that the comparator's random offset is $46.3\ \mu\mathrm{V}$ and its response time is 137 ns when the hysteresis is set to zero. The static current consumption is $11.2\ \mu\mathrm{A}$ from a 3.3-V power supply. All the hysteresis levels are obtained with good precision.