P. Manos, F. Pintchovski, J. Klein, E. Travis, B. Boeck, M. Woo, C. Chen, S. Koenigseder, R. Dillard
{"title":"A submicron triple-level-metal gate array process utilizing tungsten for 1st level interconnect","authors":"P. Manos, F. Pintchovski, J. Klein, E. Travis, B. Boeck, M. Woo, C. Chen, S. Koenigseder, R. Dillard","doi":"10.1109/VMIC.1989.78074","DOIUrl":null,"url":null,"abstract":"A novel triple-level-metal process, utilizing tungsten for first-level metallization, has been developed for use in submicron arrays. The contact barrier is a composite layer of sputtered and CVD TiN, providing for good adhesion of the blanket tungsten layer. Other process modules include tapered contact and via etches, dyed resist for fine-line patterning, reflowed BPSG for first ILD and via-1, and low-stress nitride passivation, providing for void-free metallization for all three layers. Prototype 1.0- mu m gate arrays have been fabricated using this technology.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VMIC.1989.78074","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
A novel triple-level-metal process, utilizing tungsten for first-level metallization, has been developed for use in submicron arrays. The contact barrier is a composite layer of sputtered and CVD TiN, providing for good adhesion of the blanket tungsten layer. Other process modules include tapered contact and via etches, dyed resist for fine-line patterning, reflowed BPSG for first ILD and via-1, and low-stress nitride passivation, providing for void-free metallization for all three layers. Prototype 1.0- mu m gate arrays have been fabricated using this technology.<>
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