A 0.0175mm2 600µW 32kHz input 307MHz output PLL with 190psrms jitter in 28nm FD-SOI

Abstract

A 32 kHz input analog phase-locked loop (PLL) is proposed which employs: (i) active capacitor multiplication technique for reducing PLL area wherein the input parasitic capacitance from the VCO is utilized for loop-filter capacitor realization, (ii) loop-filter noise reduction technique for lowering its noise contribution on integrated jitter at PLL output and (iii) charge-pump leakage reduction technique for improving reference-spur performance. Realized in 28nm UTBB FD-SOI process, the PLL outputs 307.2MHz clock, provides an integrated jitter of 190psrms, has reference spur of -59.5dB, occupies 0.0175mm2 area and consumes 600μW power. The PLL has an FOM of -196.6dB.